12-Bit High Speed Multiplying
D/A Converter
a
DAC312
FEATURES
P IN CO NNECTIO NS
Differential Nonlinearity: ؎1/ 2 LSB
Nonlinearity: 0.05%
Fast Settling Tim e: 250 ns
20-P in H er m etic D IP (R-Suffix),
20-P in P lastic D IP (P -Suffix),
20-P in SO L (S-Suffix)
High Com pliance: –5 V to +10 V
Differential Outputs: 0 to 4 m A
Guaranteed Monotonicity: 12 Bits
Low Full-Scale Tem pco: 10 ppm / ؇C
Circuit Interface to TTL, CMOS, ECL, PMOS/ NMOS
Low Pow er Consum ption: 225 m W
Industry Standard AM6012 Pinout
Available In Die Form
GENERAL D ESCRIP TIO N
T he DAC312 series of 12-bit multiplying digital-to-analog con-
verters provide high speed with guaranteed performance to
0.012% differential nonlinearity over the full commercial oper-
ating temperature range.
High compliance and low drift characteristics (as low as
10 ppm/°C) are also features of the DAC312 along with an ex-
cellent power supply rejection ratio of ±.001% FS/%∆V. Oper-
ating over a power supply range of +5/–11 V to ±18 V the
device consumes 225 mW at the lower supply voltages with an
absolute maximum dissipation of 375 mW at the higher supply
levels.
T he DAC312 combines a 9-bit master D/A converter with a
3-bit (MSBs) segment generator to form an accurate 12-bit D/A
converter at low cost. T his technique guarantees a very uniform
step size (up to ±1/2 LSB from the ideal), monotonicity to
12-bits and integral nonlinearity to 0.05% at its differential cur-
rent outputs. In order to provide the same performance with a
12-bit R-2R ladder design, an integral nonlinearity over tem-
perature of 1/2 LSB (0.012%) would be required.
With their guaranteed specifications, single chip reliability and
low cost, the DAC312 device makes excellent building blocks
for A/D converters, data acquisition systems, video display driv-
ers, programmable test equipment and other applications where
low power consumption and complete input/output versatility
are required.
T he 250 ns settling time with low glitch energy and low power
consumption are achieved by careful attention to the circuit de-
sign and stringent process controls. Direct interface with all
popular logic families is achieved through the logic threshold
terminal.
FUNCTIO NAL BLO CK D IAGRAM
REV. C
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use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
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© Analog Devices, Inc., 1996
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