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ADM1166ACPZ PDF预览

ADM1166ACPZ

更新时间: 2024-01-21 17:27:52
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
32页 498K
描述
Super Sequencer with Margining Control and Nonvolatile Fault Recording

ADM1166ACPZ 技术参数

是否无铅: 含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:QFP
包装说明:TFQFP, TQFP48,.35SQ针数:48
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.17
可调阈值:NO模拟集成电路 - 其他类型:POWER SUPPLY MANAGEMENT CIRCUIT
JESD-30 代码:S-PQFP-G48JESD-609代码:e3
长度:7 mm湿度敏感等级:3
信道数量:1功能数量:1
端子数量:48最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:TFQFP封装等效代码:TQFP48,.35SQ
封装形状:SQUARE封装形式:FLATPACK, THIN PROFILE, FINE PITCH
峰值回流温度(摄氏度):260电源:3/14.4,3.3/5 V
认证状态:Not Qualified座面最大高度:1.2 mm
子类别:Power Management Circuits最大供电电流 (Isup):6 mA
最大供电电压 (Vsup):5.4 V最小供电电压 (Vsup):2.7 V
标称供电电压 (Vsup):4.75 V表面贴装:YES
温度等级:INDUSTRIAL端子面层:MATTE TIN
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:40
宽度:7 mmBase Number Matches:1

ADM1166ACPZ 数据手册

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Super Sequencer with Margining Control  
and Nonvolatile Fault Recording  
ADM1166  
FUNCTIONAL BLOCK DIAGRAM  
FEATURES  
AUX1 AUX2  
REFIN  
REFOUT REFGND SDA SCL A1  
A0  
Complete supervisory and sequencing solution for up to  
10 supplies  
16 event deep black box nonvolatile fault recording  
10 supply fault detectors enable supervision of supplies to  
<0.5% accuracy at all voltages at 25°C  
ADM1166  
SMBus  
INTERFACE  
VREF  
12-BIT  
SAR ADC  
EEPROM  
<1.0% accuracy across all voltages and temperatures  
5 selectable input attenuators allow supervision of supplies to  
14.4 V on VH  
CLOSED-LOOP  
FAULT RECORDING  
MARGINING SYSTEM  
VX1  
VX2  
VX3  
VX4  
VX5  
PDO1  
PDO2  
PDO3  
PDO4  
PDO5  
PDO6  
CONFIGURABLE  
OUTPUT  
DRIVERS  
DUAL-  
FUNCTION  
INPUTS  
6 V on VP1 to VP4 (VPx)  
(LOGIC INPUTS  
OR  
(HV CAPABLE OF  
DRIVING GATES  
OF N-FET)  
5 dual-function inputs, VX1 to VX5 (VXx)  
High impedance input to supply fault detector with  
thresholds between 0.573 V and 1.375 V  
General-purpose logic input  
10 programmable driver outputs, PDO1 to PDO10 (PDOx)  
Open-collector with external pull-up  
SFDs)  
SEQUENCING  
ENGINE  
VP1  
VP2  
VP3  
VP4  
VH  
PDO7  
PDO8  
PDO9  
CONFIGURABLE  
OUTPUT  
DRIVERS  
PROGRAMMABLE  
RESET  
GENERATORS  
(LV CAPABLE  
OF DRIVING  
LOGIC SIGNALS)  
(SFDs)  
PDO10  
Push/pull output, driven to VDDCAP or VPx  
Open collector with weak pull-up to VDDCAP or VPx  
Internally charge-pumped high drive for use with external  
N-FET (PDO1 to PDO6 only)  
AGND  
PDOGND  
VDDCAP  
VDD  
ARBITRATOR  
VOUT VOUT VOUT VOUT VOUT VOUT  
DAC DAC DAC DAC DAC DAC  
DAC1 DAC2 DAC3 DAC4 DAC5 DAC6  
VCCP GND  
Sequencing engine (SE) implements state machine control of  
PDO outputs  
Figure 1.  
State changes conditional on input events  
Enables complex control of boards  
Power-up and power-down sequence control  
Fault event handling  
APPLICATIONS  
Central office systems  
Servers/routers  
Multivoltage system line cards  
DSP/FPGA supply sequencing  
In-circuit testing of margined supplies  
Interrupt generation on warnings  
Watchdog function can be integrated in SE  
Program software control of sequencing through SMBus  
Complete voltage-margining solution for 6 voltage rails  
6 voltage output 8-bit DACs (0.300 V to 1.551 V) allow voltage  
adjustment via dc-to-dc converter trim/feedback node  
12-bit ADC for readback of all supervised voltages  
2 auxiliary (single-ended) ADC inputs  
Reference input (REFIN) has 2 input options  
Driven directly from 2.048 V ( 0.25%) REFOUT pin  
More accurate external reference for improved ADC  
performance  
Device powered by the highest of VPx, VH for improved  
redundancy  
User EEPROM: 256 bytes  
Industry-standard 2-wire bus interface (SMBus)  
Guaranteed PDO low with VH, VPx = 1.2 V  
Available in 40-lead, 6 mm × 6 mm LFCSP and  
48-lead, 7 mm × 7 mm TQFP packages  
GENERAL DESCRIPTION  
The ADM1166 Super Sequencer® is a configurable supervisory/  
sequencing device that offers a single-chip solution for supply  
monitoring and sequencing in multiple-supply systems. In addition  
to these functions, the ADM1166 integrates a 12-bit ADC and  
six 8-bit voltage output DACs. These circuits can be used to  
implement a closed-loop margining system that enables supply  
adjustment by altering either the feedback node or reference of  
a dc-to-dc converter using the DAC outputs.  
Supply margining can be performed with a minimum of external  
components. The margining loop can be used for in-circuit testing  
of a board during production (for example, to verify board func-  
tionality at −5% of nominal supplies), or it can be used dynamically  
to accurately control the output voltage of a dc-to-dc converter.  
For more information about the ADM1166 register map,  
refer to the AN-698 Application Note  
Rev. 0  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rights of third parties that may result from its use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks and registeredtrademarks arethe property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Fax: 781.461.3113  
www.analog.com  
©2010 Analog Devices, Inc. All rights reserved.  
 

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