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ADM1063ACPZ-REEL7 PDF预览

ADM1063ACPZ-REEL7

更新时间: 2024-01-18 10:16:22
品牌 Logo 应用领域
亚德诺 - ADI 电源电路电源管理电路监控
页数 文件大小 规格书
36页 402K
描述
Multisupply Supervisor/Sequencer with ADC and Temperature Monitoring

ADM1063ACPZ-REEL7 技术参数

是否无铅:含铅是否Rohs认证:符合
生命周期:Active零件包装代码:QFN
包装说明:HVQCCN, LCC40,.24SQ,20针数:40
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.17
Is Samacsys:N可调阈值:NO
模拟集成电路 - 其他类型:POWER SUPPLY SUPPORT CIRCUITJESD-30 代码:S-XQCC-N40
JESD-609代码:e3长度:6 mm
湿度敏感等级:3信道数量:10
功能数量:1端子数量:40
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:UNSPECIFIED封装代码:HVQCCN
封装等效代码:LCC40,.24SQ,20封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):260
电源:3/5 V认证状态:Not Qualified
座面最大高度:1 mm子类别:Power Management Circuits
最大供电电流 (Isup):6 mA表面贴装:YES
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:40
宽度:6 mmBase Number Matches:1

ADM1063ACPZ-REEL7 数据手册

 浏览型号ADM1063ACPZ-REEL7的Datasheet PDF文件第2页浏览型号ADM1063ACPZ-REEL7的Datasheet PDF文件第3页浏览型号ADM1063ACPZ-REEL7的Datasheet PDF文件第4页浏览型号ADM1063ACPZ-REEL7的Datasheet PDF文件第5页浏览型号ADM1063ACPZ-REEL7的Datasheet PDF文件第6页浏览型号ADM1063ACPZ-REEL7的Datasheet PDF文件第7页 
Multisupply Supervisor/Sequencer  
with ADC and Temperature Monitoring  
ADM1063  
FEATURES  
FUNCTIONAL BLOCK DIAGRAM  
D1P D1N D2P D2N  
REFIN REFOUT REFGND SDA SCL A1  
A0  
Complete supervisory and sequencing solution for up to  
10 supplies  
10 supply fault detectors enable supervision of supplies to  
better than 1% accuracy  
SMBus  
INTERFACE  
VREF  
TEMP  
SENSOR  
INTERNAL  
DIODE  
5 selectable input attenuators allow supervision of  
supplies up to  
ADM1063  
12-BIT  
SAR ADC  
EEPROM  
14.4 V on VH  
CLOSED-LOOP  
MARGINING SYSTEM  
6 V on VP1 to VP4  
5 dual-function inputs, VX1 to VX5  
High impedance input to supply fault detector with  
thresholds between 0.573 V and 1.375 V  
General-purpose logic input  
10 programmable output drivers, PDO1 to PDO10  
Open collector with external pull-up  
Push/pull output, driven to VDDCAP or VPn  
Open collector with weak pull-up to VDDCAP or VPn  
Internally charge-pumped high drive for use with external  
N-FET (PDO1 to PDO6 only)  
Sequencing engine (SE) implements state machine control of  
PDO outputs  
CONFIGURABLE  
OUTPUT  
DRIVERS  
VX1  
VX2  
VX3  
VX4  
VX5  
PDO1  
PDO2  
PDO3  
PDO4  
PDO5  
PDO6  
DUAL-  
FUNCTION  
INPUTS  
(HV CAPABLE  
OF DRIVING  
GATES OF  
(LOGIC INPUTS  
OR  
SFDs)  
N-CHANNEL FET)  
SEQUENCING  
ENGINE  
VP1  
VP2  
VP3  
VP4  
VH  
PDO7  
PDO8  
PDO9  
CONFIGURABLE  
OUTPUT  
DRIVERS  
PROGRAMMABLE  
RESET  
GENERATORS  
(LV CAPABLE  
OF DRIVING  
LOGIC SIGNALS)  
(SFDs)  
PDO10  
AGND  
PDOGND  
VDDCAP  
VDD  
ARBITRATOR  
State changes conditional on input events  
Enables complex control of boards  
VCCP GND  
Power-up and power-down sequence control  
Fault event handling  
Figure 1.  
Interrupt generation on warnings  
Watchdog function can be integrated in SE  
Program software control of sequencing through SMBus  
Complete voltage margining solution for 6 voltage rails  
APPLICATIONS  
Central office systems  
Servers/routers  
6 voltage output, 8-bit DACs (0.300 V to 1.551 V) allow voltage  
adjustment via dc-to-dc converter trim/feedback node  
Multivoltage system line cards  
DSP/FPGA supply sequencing  
12-bit ADC for readback of all supervised voltages  
1 internal and 2 external temperature sensors  
Reference input, REFIN, has 2 input options  
Driven directly from 2.048 V ( 0.25%) REFOUT pin  
In-circuit testing of margined supplies  
GENERAL DESCRIPTION  
More accurate external reference for improved  
ADC performance  
Device powered by the highest of VP1 to VP4, VH for  
improved redundancy  
User EEPROM: 256 bytes  
Industry-standard, 2-wire bus interface (SMBus)  
Guaranteed PDO low with VH, VPn = 1.2 V  
The ADM1063 is a configurable supervisory/sequencing device  
that offers a single-chip solution for supply monitoring and  
sequencing in multiple supply systems. In addition to these  
functions, the ADM1063 integrates a 12-bit ADC and six 8-bit  
voltage output DACs. These circuits can be used to implement a  
closed-loop margining system, which enables supply adjustment  
by altering either the feedback node or reference of a dc-to-dc  
converter using the DAC outputs.  
40-lead, 6 mm × 6 mm LFCSP and  
48-lead, 7 mm × 7 mm TQFP packages  
(continued on Page 3)  
Rev. 0  
Information furnished by Analog Devices is believed to be accurate and reliable.  
However, no responsibility is assumed by Analog Devices for its use, nor for any  
infringements of patents or other rights of third parties that may result from its use.  
Specifications subject to change without notice. No license is granted by implication  
or otherwise under any patent or patent rights of Analog Devices. Trademarks and  
registered trademarks are the property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Fax: 781.461.3113  
www.analog.com  
© 2005 Analog Devices, Inc. All rights reserved.  

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