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ADF4218 PDF预览

ADF4218

更新时间: 2024-01-10 02:36:37
品牌 Logo 应用领域
亚德诺 - ADI 射频
页数 文件大小 规格书
20页 220K
描述
Dual RF PLL Frequency Synthesizers

ADF4218 技术参数

是否无铅: 含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:TSSOP
包装说明:TSSOP,针数:20
Reach Compliance Code:compliantECCN代码:5A991.B
HTS代码:8542.39.00.01风险等级:5.12
其他特性:ALSO REQUIRES A 3V TO 5.5V SUPPLY模拟集成电路 - 其他类型:PLL FREQUENCY SYNTHESIZER
JESD-30 代码:R-PDSO-G20JESD-609代码:e3
长度:6.5 mm湿度敏感等级:1
功能数量:1端子数量:20
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):260认证状态:Not Qualified
座面最大高度:1.2 mm最大供电电压 (Vsup):3.3 V
最小供电电压 (Vsup):2.6 V标称供电电压 (Vsup):3 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:40宽度:4.4 mm
Base Number Matches:1

ADF4218 数据手册

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a
Dual RF PLL Frequency Synthesizers  
ADF4216/ADF4217/ADF4218  
GENERAL DESCRIPTION  
FEATURES  
The ADF4216/ADF4217/ADF4218 are dual frequency synthe-  
sizers that can be used to implement local oscillators (LOs) in  
the upconversion and downconversion sections of wireless  
receivers and transmitters. They can provide the LO for both  
the RF and IF sections. They consist of a low-noise digital PFD  
(Phase Frequency Detector), a precision charge pump, a pro-  
grammable reference divider, programmable A and B counters,  
and a dual-modulus prescaler (P/P+1). The A (6-bit) and B  
(11-bit) counters, in conjunction with the dual modulus prescaler  
(P/P+1), implement an N divider (N = BP + A). In addition,  
the 14-bit reference counter (R Counter), allows selectable  
REFIN frequencies at the PFD input. A complete PLL (Phase-  
Locked Loop) can be implemented if the synthesizers are  
used with an external loop filter and VCOs (Voltage Con-  
trolled Oscillators).  
ADF4216: 550 MHz/1.2 GHz  
ADF4217: 550 MHz/2.0 GHz  
ADF4218: 550 MHz/2.5 GHz  
2.7 V to 5.5 V Power Supply  
Selectable Charge Pump Currents  
Selectable Dual Modulus Prescaler  
IF: 8/9 or 16/17  
RF: 32/33 or 64/65  
3-Wire Serial Interface  
Power-Down Mode  
APPLICATIONS  
Wireless Handsets (GSM, PCS, DCS, CDMA, WCDMA)  
Base Stations for Wireless Radio (GSM, PCS, DCS,  
CDMA, WCDMA)  
Wireless LANS  
Communications Test Equipment  
CATV Equipment  
Control of all the on-chip registers is via a simple 3-wire interface.  
The devices operate with a power supply ranging from 2.7 V  
to 5.5 V and can be powered down when not in use.  
FUNCTIONAL BLOCK DIAGRAM  
V
1
V
2
V 1  
V 2  
P
DD  
DD  
P
ADF4216/ADF4217/ADF4218  
N = BP + A  
11-BIT IF  
B-COUNTER  
PHASE  
COMPARATOR  
IF  
IF  
A
B
IN  
IF  
PRESCALER  
CHARGE  
PUMP  
CP  
IF  
IN  
6-BIT IF  
A-COUNTER  
IF  
LOCK  
DETECT  
REF  
OSCILLATOR  
IN  
14-BIT IF  
R-COUNTER  
OUTPUT  
MUX  
MUXOUT  
CLOCK  
DATA  
LE  
22-BIT  
DATA  
REGISTER  
SDOUT  
14-BIT IF  
R-COUNTER  
RF  
LOCK  
DETECT  
N = BP + A  
11-BIT RF  
B-COUNTER  
RF  
RF  
A
B
IN  
RF  
CHARGE  
PUMP  
PRESCALER  
CP  
RF  
IN  
6-BIT RF  
A-COUNTER  
PHASE  
COMPARATOR  
DGND  
RF  
AGND  
RF  
DGND  
IF  
DGND  
IF  
AGND  
IF  
REV. 0  
Information furnished by Analog Devices is believed to be accurate and  
reliable. However, no responsibility is assumed by Analog Devices for its  
use, nor for any infringements of patents or other rights of third parties  
which may result from its use. No license is granted by implication or  
otherwise under any patent or patent rights of Analog Devices.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781/329-4700  
Fax: 781/326-8703  
World Wide Web Site: http://www.analog.com  
© Analog Devices, Inc., 2000  

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