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ADF4153BRUZ-RL

更新时间: 2024-01-05 01:00:27
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亚德诺 - ADI /
页数 文件大小 规格书
24页 354K
描述
Fractional-N Frequency Synthesizer

ADF4153BRUZ-RL 数据手册

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Fractional-N Frequency Synthesizer  
Data Sheet  
ADF4153  
FEATURES  
GENERAL DESCRIPTION  
RF bandwidth to 4 GHz  
2.7 V to 3.3 V power supply  
The ADF4153 is a fractional-N frequency synthesizer  
that implements local oscillators in the upconversion  
and downconversion sections of wireless receivers and  
transmitters. It consists of a low noise digital phase  
frequency detector (PFD), a precision charge pump, and  
a programmable reference divider. There is a Σ-Δ based  
fractional interpolator to allow programmable fractional-N  
division. The INT, FRAC, and MOD registers define an  
overall N divider (N = (INT + (FRAC/MOD))). In addition,  
the 4-bit reference counter (R counter) allows selectable  
REFIN frequencies at the PFD input. A complete phase-  
locked loop (PLL) can be implemented if the synthesizer is  
used with an external loop filter and a voltage controlled  
oscillator (VCO).  
Separate VP allows extended tuning voltage  
Y version available: −40°C to +125°C  
Programmable fractional modulus  
Programmable charge pump currents  
3-wire serial interface  
Analog and digital lock detect  
Power-down mode  
Pin-compatible with ADF4110/ADF4111/ADF4112/ADF4113  
and ADF4106  
Consistent RF output phase  
Loop filter design possible with ADIsimPLL  
Qualified for automotive applications  
A simple 3-wire interface controls all on-chip registers.  
The device operates with a power supply ranging from  
2.7 V to 3.3 V and can be powered down when not in use.  
APPLICATIONS  
CATV equipment  
Base stations for mobile radio (GSM, PCS, DCS, WiMAX,  
SuperCell 3G, CDMA, W-CDMA)  
Wireless handsets (GSM, PCS, DCS, CDMA, W-CDMA)  
Wireless LANs, PMR  
Communications test equipment  
FUNCTIONAL BLOCK DIAGRAM  
AV  
DD  
DV  
DD  
V
SDV  
R
SET  
P
DD  
ADF4153  
REFERENCE  
4-BIT  
R COUNTER  
×2  
REF  
IN  
DOUBLER  
+
PHASE  
CP  
CHARGE  
PUMP  
FREQUENCY  
DETECTOR  
V
DD  
HIGH-Z  
DGND  
LOCK  
DETECT  
CURRENT  
SETTING  
OUTPUT  
MUX  
V
MUXOUT  
DD  
R
DIV  
DIV  
RFCP3 RFCP2 RFCP1  
N
RF  
RF  
A
B
IN  
N-COUNTER  
IN  
THIRD ORDER  
FRACTIONAL  
INTERPOLATOR  
CLK  
DATA  
LE  
FRACTION  
REG  
MODULUS  
REG  
INTEGER  
REG  
24-BIT  
DATA  
REGISTER  
AGND  
DGND  
CPGND  
Figure 1.  
Rev. F  
Document Feedback  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rightsof third parties that may result fromits use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks andregisteredtrademarks are the property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700 ©2003–2013 Analog Devices, Inc. All rights reserved.  
Technical Support  
www.analog.com  
 
 
 
 

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