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ADF4153

更新时间: 2024-02-22 19:00:12
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
24页 257K
描述
Fractional-N Frequency Synthesizer

ADF4153 技术参数

是否无铅: 含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP, TSSOP16,.25针数:16
Reach Compliance Code:unknownECCN代码:5A991.B
HTS代码:8542.39.00.01风险等级:5.43
模拟集成电路 - 其他类型:PLL FREQUENCY SYNTHESIZERJESD-30 代码:R-PDSO-G16
JESD-609代码:e3长度:5 mm
湿度敏感等级:1功能数量:1
端子数量:16最高工作温度:125 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP16,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):260电源:3,3/5.5 V
认证状态:Not Qualified座面最大高度:1.2 mm
子类别:PLL or Frequency Synthesis Circuits最大供电电流 (Isup):24 mA
最大供电电压 (Vsup):3.3 V最小供电电压 (Vsup):2.7 V
标称供电电压 (Vsup):3 V表面贴装:YES
技术:BICMOS温度等级:AUTOMOTIVE
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:4.4 mm
Base Number Matches:1

ADF4153 数据手册

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Fractional-N Frequency Synthesizer  
ADF4153  
FEATURES  
GENERAL DESCRIPTION  
RF bandwidth 500 MHz to 4 GHz  
2.7 V to 3.3 V power supply  
The ADF4153 is a fractional-N frequency synthesizer that  
implements local oscillators in the upconversion and  
downconversion sections of wireless receivers and transmitters.  
It consists of a low noise digital phase frequency detector  
(PFD), a precision charge pump, and a programmable reference  
divider. There is a Σ-Δ based fractional interpolator to allow  
programmable fractional-N division. The INT, FRAC, and  
MOD registers define an overall N divider (N = (INT +  
(FRAC/MOD))). In addition, the 4-bit reference counter (R  
counter) allows selectable REFIN frequencies at the PFD input.  
A complete phase-locked loop (PLL) can be implemented if the  
synthesizer is used with an external loop filter and a voltage  
controlled oscillator (VCO).  
Separate VP allows extended tuning voltage  
Programmable dual-modulus prescaler 4/5, 8/9  
Programmable charge pump currents  
3-wire serial interface  
Analog and digital lock detect  
Power-down mode  
Pin compatible with the  
ADF4110/ADF4111/ADF4112/ADF4113 and ADF4106  
Programmable modulus on fractional-N synthesizer  
Trade-off noise versus spurious performance  
APPLICATIONS  
CATV equipment  
Base stations for mobile radio (GSM, PCS, DCS,  
CDMA, WCDMA)  
Wireless handsets (GSM, PCS, DCS, CDMA, WCDMA)  
Wireless LANs  
Control of all on-chip registers is via a simple 3-wire interface.  
The device operate with a power supply ranging from 2.7 V to  
3.3 V and can be powered down when not in use.  
Communications test equipment  
FUNCTIONAL BLOCK DIAGRAM  
AV  
DV  
V
SDV  
R
SET  
DD  
DD  
P
DD  
ADF4153  
REFERENCE  
4-BIT  
R COUNTER  
×2  
REF  
IN  
DOUBLER  
+
PHASE  
CP  
CHARGE  
PUMP  
FREQUENCY  
DETECTOR  
V
DD  
HIGH Z  
DGND  
LOCK  
DETECT  
CURRENT  
SETTING  
OUTPUT  
MUX  
MUXOUT  
V
R
N
DD  
DIV  
RFCP3 RFCP2 RFCP1  
DIV  
RF  
RF  
A
B
IN  
N-COUNTER  
IN  
THIRD ORDER  
FRACTIONAL  
INTERPOLATOR  
CLOCK  
DATA  
LE  
FRACTION  
REG  
MODULUS  
REG  
INTEGER  
REG  
24-BIT  
DATA  
REGISTER  
AGND  
DGND  
CPGND  
Figure 1.  
Rev. A  
Information furnished by Analog Devices is believed to be accurate and reliable.  
However, no responsibility is assumed by Analog Devices for its use, nor for any  
infringements of patents or other rights of third parties that may result from its use.  
Specifications subject to change without notice. No license is granted by implication  
or otherwise under any patent or patent rights of Analog Devices. Trademarks and  
registered trademarks are the property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Fax: 781.326.8703  
www.analog.com  
© 2004 Analog Devices, Inc. All rights reserved.  

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