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ADF4150HV PDF预览

ADF4150HV

更新时间： 2024-01-03 11:03:04
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
28页 629K
描述
High Voltage, Fractional-N

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ADF4150HV 技术参数

是否无铅： 含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：QFN
包装说明：HVQCCN, LCC32,.2SQ,20针数：32
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：2.22
Is Samacsys：N模拟集成电路 - 其他类型：PLL FREQUENCY SYNTHESIZER
JESD-30 代码：S-XQCC-N32JESD-609代码：e3
长度：5 mm功能数量：1
端子数量：32最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：UNSPECIFIED
封装代码：HVQCCN封装等效代码：LCC32,.2SQ,20
封装形状：SQUARE封装形式：CHIP CARRIER
峰值回流温度（摄氏度）：260电源：3.3 V
认证状态：Not Qualified座面最大高度：0.8 mm
子类别：PLL or Frequency Synthesis Circuits最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES温度等级：INDUSTRIAL
端子面层：MATTE TIN端子形式：NO LEAD
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：40宽度：5 mm
Base Number Matches：1

ADF4150HV 数据手册

 浏览型号ADF4150HV的Datasheet PDF文件第2页浏览型号ADF4150HV的Datasheet PDF文件第3页浏览型号ADF4150HV的Datasheet PDF文件第4页浏览型号ADF4150HV的Datasheet PDF文件第5页浏览型号ADF4150HV的Datasheet PDF文件第6页浏览型号ADF4150HV的Datasheet PDF文件第7页 
High Voltage, Fractional-N/  
Integer-N PLL Synthesizer  
ADF4150HV  
FEATURES  
GENERAL DESCRIPTION  
Fractional-N synthesizer and integer-N synthesizer  
High voltage charge pump: VP = 6 V to 30 V  
Tuning range: 1.0 V to 29 V (or 1 V from VP supply rails)  
RF bandwidth to 3.0 GHz  
Programmable divide-by-1/-2/-4/-8/-16 outputs  
Synthesizer power supply: 3.0 V to 3.6 V  
Programmable dual-modulus prescaler of 4/5 or 8/9  
Programmable output power level  
The ADF4150HV is a 3.0 GHz, fractional-N or integer-N  
frequency synthesizer with an integrated high voltage charge  
pump. The synthesizer can be used to drive external wideband  
VCOs directly, eliminating the need for operational amplifiers  
to achieve higher tuning voltages. This simplifies design and  
reduces cost while improving phase noise, in contrast to active  
filter topologies, which tend to degrade phase noise compared  
to passive filter topologies.  
Programmable charge pump currents  
RF output mute function  
3-wire serial interface  
The VCO frequency can be divided by 1, 2, 4, 8, or 16 to allow  
the user to generate RF output frequencies as low as 31.25 MHz.  
For applications that require isolation, the RF output stage can be  
muted. The mute function is both pin- and software-controllable.  
Analog and digital lock detect  
APPLICATIONS  
A simple 3-wire interface controls all on-chip registers. The  
charge pump operates from a power supply ranging from 6 V to  
30 V, whereas the rest of the device operates from 3.0 V to 3.6 V.  
The ADF4150HV can be powered down when not in use.  
Wireless infrastructure  
Microwave point-to-point/point-to-multipoint radios  
VSAT radios  
Test equipment  
Private land mobile radios  
FUNCTIONAL BLOCK DIAGRAM  
SDV  
AV  
DV  
V
R
SET  
DD  
DD  
DD  
P
MULTIPLEXER  
MUXOUT  
LD  
10-BIT R  
COUNTER  
÷2  
DIVIDER  
×2  
REF  
DOUBLER  
IN  
LOCK  
DETECT  
CLK  
DATA  
LE  
DATA REGISTER  
HIGH VOLTAGE  
CHARGE  
FUNCTION  
LATCH  
CP  
OUT  
PUMP  
PHASE  
COMPARATOR  
BOOST  
MODE  
CURRENT  
SETTING  
RF  
RF  
+
–
OUT  
OUT  
OUTPUT  
STAGE  
DIVIDE-BY-1/  
-2/-4/-8/-16  
INTEGER  
VALUE  
FRACTION  
VALUE  
MODULUS  
VALUE  
PDB  
RF  
THIRD-ORDER  
FRACTIONAL  
INTERPOLATOR  
RF  
+
–
RF  
INPUT  
IN  
MULTIPLEXER  
RF  
IN  
N COUNTER  
ADF4150HV  
CE  
GND  
CP  
SD  
GND  
GND  
Figure 1.  
Rev. 0  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rights of third parties that may result from its use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks and registeredtrademarks arethe property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Fax: 781.461.3113  
www.analog.com  
©2011 Analog Devices, Inc. All rights reserved.  
 
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