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ADF4002

更新时间： 2024-02-01 06:03:09
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
24页 457K
描述
Phase Detector/Frequency Synthesizer

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ADF4002 技术参数

是否无铅： 含铅是否Rohs认证： 符合
生命周期：Active包装说明：TSSOP, TSSOP16,.25
针数：16Reach Compliance Code：compliant
风险等级：5.65模拟集成电路 - 其他类型：PLL FREQUENCY SYNTHESIZER
JESD-30 代码：R-PDSO-G16长度：5 mm
功能数量：1端子数量：16
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP16,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH座面最大高度：1.2 mm
最大供电电流 (Isup)：6 mA最大供电电压 (Vsup)：3.3 V
最小供电电压 (Vsup)：2.7 V标称供电电压 (Vsup)：3 V
表面贴装：YES技术：BICMOS
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
宽度：4.4 mmBase Number Matches：1

ADF4002 数据手册

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Phase Detector/Frequency Synthesizer  
ADF4002  
FEATURES  
GENERAL DESCRIPTION  
400 MHz bandwidth  
2.7 V to 3.3 V power supply  
Separate charge pump supply (VP) allows extended  
tuning voltage in 3 V systems  
Programmable charge pump currents  
3-wire serial interface  
Analog and digital lock detect  
Hardware and software power-down mode  
200 MHz phase detector  
The ADF4002 frequency synthesizer is used to implement local  
oscillators in the upconversion and downconversion sections of  
wireless receivers and transmitters. It consists of a low-noise  
digital phase frequency detector (PFD), a precision charge  
pump, a programmable reference divider, and programmable  
N divider. The 14-bit reference counter (R counter), allows  
selectable REFIN frequencies at the PFD input. A complete  
phase-locked loop (PLL) can be implemented if the synthesizer  
is used with an external loop filter and voltage controlled  
oscillator (VCO). In addition, by programming R and N to 1,  
the part can be used as a stand alone PFD and charge pump.  
APPLICATIONS  
Clock conditioning  
Clock generation  
IF LO generation  
FUNCTIONAL BLOCK DIAGRAM  
AV  
DV  
R
SET  
V
CPGND  
DD  
DD  
P
REFERENCE  
14-BIT  
R COUNTER  
PHASE  
FREQUENCY  
DETECTOR  
REF  
CHARGE  
PUMP  
IN  
CP  
14  
R COUNTER  
LATCH  
LOCK  
DETECT  
CURRENT  
SETTING 2  
CURRENT  
SETTING 1  
CLK  
DATA  
LE  
24-BIT INPUT  
REGISTER  
FUNCTION  
LATCH  
CPI6 CPI5 CPI4  
HIGH Z  
CPI3 CPI2 CPI1  
22  
N COUNTER  
LATCH  
SD  
OUT  
AV  
DD  
MUXOUT  
MUX  
SD  
OUT  
RF  
RF  
A
B
13-BIT  
N COUNTER  
IN  
IN  
M3 M2 M1  
ADF4002  
CE  
AGND DGND  
Figure 1.  
Rev. 0  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rights of third parties that may result from its use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks and registeredtrademarks arethe property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Fax: 781.461.3113  
www.analog.com  
©2006 Analog Devices, Inc. All rights reserved.  
 
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