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ADCLK944BCPZ-R7 PDF预览

ADCLK944BCPZ-R7

更新时间: 2024-02-25 01:51:19
品牌 Logo 应用领域
亚德诺 - ADI 时钟驱动器逻辑集成电路PC
页数 文件大小 规格书
12页 217K
描述
2.5 V/3.3 V, Four LVPECL Outputs, SiGe Clock Fanout Buffer

ADCLK944BCPZ-R7 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:QFN
包装说明:HVQCCN,针数:16
Reach Compliance Code:unknown风险等级:5.74
Is Samacsys:N系列:2400
输入调节:DIFFERENTIALJESD-30 代码:S-PQCC-N16
JESD-609代码:e3长度:3 mm
逻辑集成电路类型:LOW SKEW CLOCK DRIVER湿度敏感等级:NOT APPLICABLE
功能数量:1反相输出次数:
端子数量:16实输出次数:4
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:HVQCCN
封装形状:SQUARE封装形式:CHIP CARRIER
峰值回流温度(摄氏度):260传播延迟(tpd):0.13 ns
认证状态:COMMERCIALSame Edge Skew-Max(tskwd):0.015 ns
座面最大高度:0.8 mm最大供电电压 (Vsup):3.63 V
最小供电电压 (Vsup):2.375 V标称供电电压 (Vsup):2.5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:MATTE TIN
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:40
宽度:3 mm最小 fmax:6200 MHz
Base Number Matches:1

ADCLK944BCPZ-R7 数据手册

 浏览型号ADCLK944BCPZ-R7的Datasheet PDF文件第2页浏览型号ADCLK944BCPZ-R7的Datasheet PDF文件第3页浏览型号ADCLK944BCPZ-R7的Datasheet PDF文件第4页浏览型号ADCLK944BCPZ-R7的Datasheet PDF文件第5页浏览型号ADCLK944BCPZ-R7的Datasheet PDF文件第6页浏览型号ADCLK944BCPZ-R7的Datasheet PDF文件第7页 
2.5 V/3.3 V, Four LVPECL Outputs,  
SiGe Clock Fanout Buffer  
ADCLK944  
FUNCTIONAL BLOCK DIAGRAM  
FEATURES  
Operating frequency: 7.0 GHz  
Broadband random jitter: 50 fs rms  
On-chip input terminations  
LVPECL  
ADCLK944  
Q0  
Q0  
Power supply (VCC − VEE): 2.5 V to 3.3 V  
V
REF  
REFERENCE  
Q1  
Q1  
Q2  
Q2  
Q3  
Q3  
APPLICATIONS  
V
T
Low jitter clock distribution  
Clock and data signal restoration  
Level translation  
Wireless communications  
Wired communications  
CLK  
CLK  
Medical and industrial imaging  
ATE and high performance instrumentation  
Figure 1.  
The ADCLK944 features four full-swing emitter-coupled logic  
(ECL) output drivers. For LVPECL (positive ECL) operation,  
bias VCC to the positive supply and VEE to ground. For ECL  
operation, bias VCC to ground and VEE to the negative supply.  
GENERAL DESCRIPTION  
The ADCLK944 is an ultrafast clock fanout buffer fabricated on  
the Analog Devices, Inc., proprietary XFCB3 silicon germanium  
(SiGe) bipolar process. This device is designed for high speed  
applications requiring low jitter.  
The ECL output stages are designed to directly drive 800 mV  
each side into 50 Ω terminated to VCC − 2 V for a total differen-  
tial output swing of 1.6 V.  
The device has a differential input equipped with center-tapped,  
differential, 100 Ω on-chip termination resistors. The input can  
accept dc-coupled LVPECL, CML, 3.3 V CMOS (single-ended),  
and ac-coupled 1.8 V CMOS, LVDS, and LVPECL inputs. A VREF  
pin is available for biasing ac-coupled inputs.  
The ADCLK944 is available in a 16-lead LFCSP and is specified  
for operation over the standard industrial temperature range of  
−40°C to +85°C.  
Rev. 0  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rights of third parties that may result from its use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks and registeredtrademarks arethe property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Fax: 781.461.3113  
www.analog.com  
©2010 Analog Devices, Inc. All rights reserved.  
 

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