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ADCLK914BCPZ-WP PDF预览

ADCLK914BCPZ-WP

更新时间： 2024-01-05 18:10:20
品牌 Logo 应用领域
亚德诺 - ADI 缓冲放大器放大器电路信息通信管理时钟
页数 文件大小 规格书
12页 304K
描述
Ultrafast, SiGe, Open-Collector HVDS Clock/Data Buffer

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ADCLK914BCPZ-WP 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：QFN
包装说明：HVQCCN,针数：16
Reach Compliance Code：unknown风险等级：5.7
Is Samacsys：N放大器类型：BUFFER
JESD-30 代码：S-XQCC-N16JESD-609代码：e3
长度：3 mm湿度敏感等级：NOT APPLICABLE
功能数量：1端子数量：16
最高工作温度：125 °C最低工作温度：-40 °C
封装主体材料：UNSPECIFIED封装代码：HVQCCN
封装形状：SQUARE封装形式：CHIP CARRIER
峰值回流温度（摄氏度）：260认证状态：COMMERCIAL
座面最大高度：0.9 mm子类别：Buffer Amplifier
供电电压上限：6 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：BICMOS
温度等级：AUTOMOTIVE端子面层：MATTE TIN
端子形式：NO LEAD端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：40
宽度：3 mmBase Number Matches：1

ADCLK914BCPZ-WP 数据手册

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Ultrafast, SiGe, Open-Collector  
HVDS Clock/Data Buffer  
ADCLK914  
FUNCTIONAL BLOCK DIAGRAM  
FEATURES  
7.5 GHz operating frequency  
160 ps propagation delay  
V
V
CC  
REF  
100 ps output rise/fall  
110 fs random jitter  
On-chip input terminations  
Extended industrial temperature range: −40°C to +125°C  
3.3 V power supply (VCC − VEE  
ADCLK914  
V
T
50Ω  
50Ω  
50Ω 50Ω  
Q
Q
D
D
)
APPLICATIONS  
Clock and data signal restoration  
High speed converter clocking  
Broadband communications  
Cellular infrastructure  
V
EE  
Figure 1.  
High speed line receivers  
ATE and high performance instrumentation  
Level shifting  
Threshold detection  
GENERAL DESCRIPTION  
The input has a center tapped, 100 Ω, on-chip termination  
resistor and accepts LVPECL, CML, CMOS, LVTTL, or LVDS  
(ac-coupled only). A VREF pin is available for biasing ac-coupled  
inputs.  
The ADCLK914 is an ultrafast clock/data buffer fabricated on  
the Analog Devices, Inc., proprietary, complementary bipolar  
(XFCB-3) silicon-germanium (SiGe) process. The ADCLK914  
features high voltage differential signaling (HVDS) outputs  
suitable for driving the latest Analog Devices high speed digital-  
to-analog converters (DACs). The ADCLK914 has a single,  
differential open-collector output.  
The HVDS output stage is designed to directly drive 1.9 V each  
side into 50 Ω terminated to VCC for a total differential output  
swing of 3.8 V.  
The ADCLK914 buffer operates up to 7.5 GHz with a 160 ps  
propagation delay and adds only 110 fs random jitter (RJ).  
The ADCLK914 is available in a 16-lead LFCSP. It is specified  
for operation over the extended industrial temperature range of  
−40°C to +125°C.  
Rev. A  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rights of third parties that may result from its use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks and registeredtrademarks arethe property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Fax: 781.461.3113  
www.analog.com  
©2008 Analog Devices, Inc. All rights reserved.  
 
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