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ADAU1761BCPZ

更新时间: 2024-01-16 17:46:20
品牌 Logo 应用领域
亚德诺 - ADI 解码器编解码器消费电路商用集成电路PC
页数 文件大小 规格书
92页 1103K
描述
SigmaDSP Stereo, Low Power, 96 kHz, 24-Bit Audio Codec with Integrated PLL

ADAU1761BCPZ 技术参数

是否无铅: 含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:QFN
包装说明:HVQCCN, LCC32,.2SQ,20针数:32
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.31.00.01风险等级:5.06
Samacsys Confidence:3Samacsys Status:Released
2D Presentation:https://componentsearchengine.com/2D/0T/563427.3.1.pngSchematic Symbol:https://componentsearchengine.com/symbol.php?partID=563427
PCB Footprint:https://componentsearchengine.com/footprint.php?partID=5634273D View:https://componentsearchengine.com/viewer/3D.php?partID=563427
Samacsys PartID:563427Samacsys Image:https://componentsearchengine.com/Images/9/ADAU1761BCPZ-RL.jpg
Samacsys Thumbnail Image:https://componentsearchengine.com/Thumbnails/3/ADAU1761BCPZ-RL.jpgSamacsys Pin Count:33
Samacsys Part Category:Integrated CircuitSamacsys Package Category:Quad Flat No-Lead
Samacsys Footprint Name:CP32-4Samacsys Released Date:2017-01-11 11:21:59
Is Samacsys:N商用集成电路类型:CONSUMER CIRCUIT
JESD-30 代码:S-XQCC-N32JESD-609代码:e3
长度:5 mm湿度敏感等级:3
功能数量:1端子数量:32
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:UNSPECIFIED封装代码:HVQCCN
封装等效代码:LCC32,.2SQ,20封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):260
电源:3.3 V认证状态:Not Qualified
座面最大高度:1 mm子类别:Other Consumer ICs
最大供电电压 (Vsup):3.65 V最小供电电压 (Vsup):1.8 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:40宽度:5 mm
Base Number Matches:1

ADAU1761BCPZ 数据手册

 浏览型号ADAU1761BCPZ的Datasheet PDF文件第2页浏览型号ADAU1761BCPZ的Datasheet PDF文件第3页浏览型号ADAU1761BCPZ的Datasheet PDF文件第4页浏览型号ADAU1761BCPZ的Datasheet PDF文件第5页浏览型号ADAU1761BCPZ的Datasheet PDF文件第6页浏览型号ADAU1761BCPZ的Datasheet PDF文件第7页 
SigmaDSP Stereo, Low Power, 96 kHz,  
24-Bit Audio Codec with Integrated PLL  
ADAU1761  
FEATURES  
GENERAL DESCRIPTION  
SigmaDSP 28-/56-bit, 50 MIPS digital audio processor  
Fully programmable with SigmaStudio graphical tool  
24-bit stereo audio ADC and DAC: >98 dB SNR  
Sampling rates from 8 kHz to 96 kHz  
The ADAU1761 is a low power, stereo audio codec with  
integrated digital audio processing that supports stereo 48 kHz  
record and playback at 14 mW from a 1.8 V analog supply. The  
stereo audio ADCs and DACs support sample rates from 8 kHz  
Low power: 7 mW record, 7 mW playback, 48 kHz at 1.8 V  
6 analog input pins, configurable for single-ended or  
differential inputs  
Flexible analog input/output mixers  
Stereo digital microphone input  
Analog outputs: 2 differential stereo, 2 single-ended stereo,  
1 mono headphone output driver  
PLL supporting input clocks from 8 MHz to 27 MHz  
Analog automatic level control (ALC)  
Microphone bias reference voltage  
to 96 kHz as well as a digital volume control.  
The SigmaDSP® core features 28-bit processing (56-bit double  
precision). The processor allows system designers to compensate  
for the real-world limitations of microphones, speakers, amplifiers,  
and listening environments, resulting in a dramatic improvement  
in the perceived audio quality through equalization, multiband  
compression, limiting, and third-party branded algorithms.  
The SigmaStudio™ graphical development tool is used to program  
the ADAU1761. This software includes audio processing blocks  
such as filters, dynamics processors, mixers, and low level DSP  
functions for fast development of custom signal flows.  
Analog and digital I/O: 1.8 V to 3.65 V  
I2C and SPI control interfaces  
Digital audio serial data I/O: stereo and time-division  
multiplexing (TDM) modes  
Software-controllable clickless mute  
Software power-down  
GPIO pins for digital controls and outputs  
32-lead, 5 mm × 5 mm LFCSP  
−40°C to +85°C operating temperature range  
The record path includes an integrated microphone bias circuit  
and six inputs. The inputs can be mixed and muxed before the  
ADC, or they can be configured to bypass the ADC. The  
ADAU1761 includes a stereo digital microphone input.  
The ADAU1761 includes five high power output drivers (two  
differential and three single-ended), supporting stereo head-  
phones, an earpiece, or other output transducer. AC-coupled  
or capless configurations are supported. Individual fine level  
controls are supported on all analog outputs. The output mixer  
stage allows for flexible routing of audio.  
APPLICATIONS  
Smartphones/multimedia phones  
Digital still cameras/digital video cameras  
Portable media players/portable audio players  
Phone accessories products  
FUNCTIONAL BLOCK DIAGRAM  
HP JACK  
DETECTION  
REGULATOR  
ADAU1761  
JACKDET/MICIN  
LAUX  
LINP  
LINN  
LOUTP  
LOUTN  
LHP  
DAC  
DAC  
ADC  
ADC  
DAC  
INPUT  
DIGITAL DIGITAL  
FILTERS FILTERS  
MIXERS  
OUTPUT  
MIXERS  
MONOOUT  
RHP  
RINP  
RINN  
ALC  
ADC  
ROUTP  
ROUTN  
RAUX  
2
I C/SPI  
CONTROL PORT  
MICROPHONE  
BIAS  
SERIAL DATA  
INPUT/OUTPUT PORTS  
MICBIAS  
PLL  
MCLK  
ADDR0/ ADDR1/ SCL/ SDA/  
CDATA CCLK COUT  
CLATCH  
Figure 1.  
Rev. C  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rights of third parties that may result from its use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks and registeredtrademarks arethe property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700 www.analog.com  
Fax: 781.461.3113 ©2009–2010 Analog Devices, Inc. All rights reserved.  
 
 
 

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