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ADAU1445YSVZ-3A

更新时间： 2024-01-17 15:27:04
品牌 Logo 应用领域
亚德诺 - ADI 商用集成电路
页数 文件大小 规格书
92页 1008K
描述
SigmaDSP Digital Audio Processor

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ADAU1445YSVZ-3A 技术参数

是否无铅： 含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：QFP
包装说明：HTFQFP, TQFP100,.63SQ针数：100
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.31.00.01风险等级：1.6
Samacsys Confidence：Samacsys Status：Released
Schematic Symbol：https://componentsearchengine.com/symbol.php?partID=578993PCB Footprint：https://componentsearchengine.com/footprint.php?partID=578993
Samacsys PartID：578993Samacsys Image：https://componentsearchengine.com/Images/9/ADAU1445YSVZ-3A-RL.jpg
Samacsys Thumbnail Image：https://componentsearchengine.com/Thumbnails/1/ADAU1445YSVZ-3A-RL.jpgSamacsys Pin Count：101
Samacsys Part Category：Integrated CircuitSamacsys Package Category：Other
Samacsys Footprint Name：QFP50P1600X1600X120-101NSamacsys Released Date：2017-01-11 11:21:59
Is Samacsys：N其他特性：IT CAN OPERATES WITH 3.3V ANALOG SUPPLY AND 1.8V DIGITAL SUPPLY
商用集成电路类型：CONSUMER CIRCUITJESD-30 代码：S-PQFP-G100
JESD-609代码：e3长度：14 mm
湿度敏感等级：1功能数量：1
端子数量：100最高工作温度：105 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：HTFQFP封装等效代码：TQFP100,.63SQ
封装形状：SQUARE封装形式：FLATPACK, HEAT SINK/SLUG, THIN PROFILE, FINE PITCH
峰值回流温度（摄氏度）：225电源：1.8,3.3 V
认证状态：Not Qualified座面最大高度：1.2 mm
子类别：Other Consumer ICs最大供电电压 (Vsup)：3.63 V
最小供电电压 (Vsup)：2.97 V表面贴装：YES
温度等级：INDUSTRIAL端子面层：MATTE TIN
端子形式：GULL WING端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：14 mmBase Number Matches：1

ADAU1445YSVZ-3A 数据手册

 浏览型号ADAU1445YSVZ-3A的Datasheet PDF文件第2页浏览型号ADAU1445YSVZ-3A的Datasheet PDF文件第3页浏览型号ADAU1445YSVZ-3A的Datasheet PDF文件第4页浏览型号ADAU1445YSVZ-3A的Datasheet PDF文件第5页浏览型号ADAU1445YSVZ-3A的Datasheet PDF文件第6页浏览型号ADAU1445YSVZ-3A的Datasheet PDF文件第7页 
SigmaDSP Digital Audio Processor  
with Flexible Audio Routing Matrix  
ADAU1442/ADAU1445/ADAU1446  
I2C and SPI control interfaces  
FEATURES  
Standalone operation  
Self-boot from serial EEPROM  
Fully programmable audio digital signal processor (DSP) for  
enhanced sound processing  
4-channel, 10-bit auxiliary control ADC  
Multipurpose pins for digital controls and outputs  
Easy implementation of available third-party algorithms  
On-chip regulator for generating 1.8 V from 3.3 V supply  
100-lead TQFP and LQFP packages  
Features SigmaStudio, a proprietary graphical programming  
tool for the development of custom signal flows  
172 MHz SigmaDSP core; 3584 instructions per sample at 48 kHz  
4k parameter RAM, 8k data RAM  
Flexible audio routing matrix (FARM)  
24-channel digital input and output  
Temperature range: −40°C to +105°C  
Up to 8 stereo asynchronous sample rate converters  
(from 1:8 up to 7.75:1 ratio and 139 dB DNR)  
Stereo S/PDIF input and output  
Supports serial and TDM I/O, up to fS = 192 kHz  
Multichannel byte-addressable TDM serial port  
Pool of 170 ms digital audio delay (at 48 kHz)  
Clock oscillator for generating master clock from crystal  
PLL for generating core clock from common audio clocks  
APPLICATIONS  
Automotive audio processing  
Head units  
Navigation systems  
Rear-seat entertainment systems  
DSP amplifiers (sound system amplifiers)  
Commercial audio processing  
FUNCTIONAL BLOCK DIAGRAM  
MP[3:0]/  
2
SPI/I C* SELFBOOT MP[11:4] ADC[3:0]  
XTALI XTALO  
ADAU1442/  
ADAU1445/  
ADAU1446  
2
I C/SPI CONTROL  
INTERFACE  
MP/  
AUX ADC  
CLOCK  
OSCILLATOR  
CLKOUT  
PLL  
AND SELF-BOOT  
1.8V  
REGULATOR  
PROGRAMMABLE AUDIO  
PROCESSOR CORE  
S/PDIF  
RECEIVER  
S/PDIF  
TRANSMITTER  
SPDIFI  
SPDIFO  
FLEXIBLE AUDIO ROUTING MATRIX  
(FARM)  
SDATA_IN[8:0]  
(24-CHANNEL  
DIGITAL AUDIO  
INPUT)  
SDATA_OUT[8:0]  
(24-CHANNEL  
DIGITAL AUDIO  
OUTPUT)  
SERIAL DATA  
INPUT PORT  
SERIAL DATA  
OUTPUT PORT  
(×9)  
UP TO 16 CHANNELS OF  
ASYNCHRONOUS  
SAMPLE RATE  
(×9)  
CONVERTERS  
†
†
BIT CLOCK  
BIT CLOCK  
(BCLK)  
(BCLK)  
SERIAL CLOCK  
DOMAINS  
†
†
(×12)  
FRAME CLOCK  
(LRCLK)  
FRAME CLOCK  
(LRCLK)  
2
*SPI/I C = THE ADDR0, CLATCH, SCL/CCLK, SDA/COUT, AND ADDR1/CDATA PINS.  
†
THERE ARE 12 BIT CLOCKS (BCLK[11:0]) AND 12 FRAME CLOCKS (LRCLK[11:0]) IN TOTAL. OF THE 12 CLOCKS,  
SIX ARE ASSIGNABLE, THREE MUST BE OUTPUTS, AND THREE MUST BE INPUTS.  
Figure 1.  
Rev. C  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rights of third parties that may result from its use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks and registeredtrademarks arethe property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Fax: 781.461.3113  
www.analog.com  
©2010 Analog Devices, Inc. All rights reserved.  
 
 
 
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