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AD9958YSV PDF预览

AD9958YSV

更新时间: 2024-02-15 00:09:55
品牌 Logo 应用领域
亚德诺 - ADI 数据分配系统
页数 文件大小 规格书
40页 1404K
描述
IC,FREQUENCY SYNTHESIZER,LLCC,56PIN,PLASTIC

AD9958YSV 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
Reach Compliance Code:unknown风险等级:5.92
JESD-30 代码:S-PQCC-N56端子数量:56
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:QCCN
封装等效代码:LCC56,.31SQ,20封装形状:SQUARE
封装形式:CHIP CARRIER电源:1.8,3.3 V
认证状态:Not Qualified子类别:PLL or Frequency Synthesis Circuits
表面贴装:YES温度等级:INDUSTRIAL
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUADBase Number Matches:1

AD9958YSV 数据手册

 浏览型号AD9958YSV的Datasheet PDF文件第2页浏览型号AD9958YSV的Datasheet PDF文件第3页浏览型号AD9958YSV的Datasheet PDF文件第4页浏览型号AD9958YSV的Datasheet PDF文件第5页浏览型号AD9958YSV的Datasheet PDF文件第6页浏览型号AD9958YSV的Datasheet PDF文件第7页 
2-Channel 500 MSPS DDS  
with 10-Bit DACs  
AD9958  
FEATURES  
APPLICATIONS  
2 synchronized DDS channels @ 500 MSPS  
Agile local oscillator  
Independent frequency/phase/amplitude control between  
channels  
Phased array radar/sonar  
Instrumentation  
Matched latencies for frequency/phase/amplitude changes  
Excellent channel-to-channel isolation (>72 dB)  
Synchronized clocking  
RF source for AOTF  
Linear frequency/phase/amplitude sweeping capability  
Up to 16 levels of frequency/phase/amplitude modulation  
(pin-selectable)  
Single-side band suppressed carrier  
Quadrature communications  
2 integrated 10-bit D/A converters (DACs)  
Individually programmable DAC full-scale currents  
32-bit frequency tuning resolution  
14-bit phase offset resolution  
10-bit output amplitude scaling resolution  
Serial I/O Port (SPI) with 800Mbps data throughput  
Software-/hardware-controlled power-down  
Dual supply operation (1.8 V DDS core/3.3 V serial I/O)  
Multiple device synchronization  
Selectable 4× to 20× REF_CLK multiplier (PLL)  
Selectable REF_CLK crystal oscillator  
56-Lead LFCSP  
FUNCTIONAL BLOCK DIAGRAM  
AD9958  
DDS CORE  
COS(X)  
IOUT  
IOUT  
Σ
Σ
Σ
Σ
DAC  
DAC  
32  
32  
32  
32  
15  
10  
10  
10  
10  
DDS CORE  
COS(X)  
IOUT  
IOUT  
Σ
Σ
15  
SCALABLE  
DAC REF  
CURRENT  
DAC_RSET  
32  
PHASE/  
PHASE  
14  
AMP/  
AMP  
10  
FTW  
FTW  
SYNC_IN  
SYNC_OUT  
I/O_UPDATE  
TIMING AND CONTROL LOGIC  
PWR_DWN_CTL  
MASTER_RESET  
SYSTEM  
CLK  
CONTROL  
REGISTERS  
÷4  
SYNC_CLK  
SCLK  
CS  
REF CLOCK  
MULTIPLIER  
4× TO 20×  
I/O  
PORT  
BUFFER  
REF_CLK  
REF_CLK  
CHANNEL  
MUX  
SDIO_0  
SDIO_1  
SDIO_2  
SDIO_3  
REGISTE  
RS  
BUFFER/  
XTAL  
OSCILLATOR  
PROFILE  
REGISTERS  
1.8V  
1.8V  
AVDD  
DVDD  
PS0 PS1 PS2 PS3  
DVDD_I/O  
CLK_MODE_SEL  
Figure 1.  
Rev. 0  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rights of third parties that may result from its use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks and registeredtrademarks arethe property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Fax: 781.461.3113  
www.analog.com  
© 2005 Analog Devices, Inc. All rights reserved.  
 

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