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AD9925 PDF预览

AD9925

更新时间: 2024-01-07 17:43:31
品牌 Logo 应用领域
亚德诺 - ADI 驱动器
页数 文件大小 规格书
96页 1940K
描述
CCD Signal Processor with Vertical Driver and Precision Timing Generator

AD9925 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Active零件包装代码:BGA
包装说明:8 X 8 MM, 0.65 MM PITCH, LEAD FREE, PLASTIC, CSBGA-96针数:96
Reach Compliance Code:unknown风险等级:5.65
Is Samacsys:N商用集成电路类型:CONSUMER CIRCUIT
JESD-30 代码:S-PBGA-B96JESD-609代码:e3
长度:8 mm湿度敏感等级:NOT SPECIFIED
功能数量:1端子数量:96
最高工作温度:85 °C最低工作温度:-25 °C
封装主体材料:PLASTIC/EPOXY封装代码:LFBGA
封装形状:SQUARE封装形式:GRID ARRAY, LOW PROFILE, FINE PITCH
峰值回流温度(摄氏度):260认证状态:COMMERCIAL
座面最大高度:1.4 mm最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):2.7 V表面贴装:YES
温度等级:OTHER端子面层:MATTE TIN
端子形式:BALL端子节距:0.65 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:40
宽度:8 mmBase Number Matches:1

AD9925 数据手册

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CCD Signal Processor with Vertical Driver  
and Precision Timing ™ Generator  
AD9925  
FEATURES  
GENERAL DESCRIPTION  
Integrated 10-channel V-driver  
The AD9925 is a complete 36 MHz front end solution for digi-  
tal still camera and other CCD imaging applications. Based on  
the AD9995 product, the AD9925 includes the analog front end  
and a fully programmable timing generator (AFETG), combined  
with a 10-channel vertical driver (V-driver). A Precision Timing  
core allows adjustment of high speed clocks with approximately  
600 ps resolution at 36 MHz operation.  
Register-compatible with the AD9991 and AD9995  
3-field (6-phase) vertical clock support  
2 additional vertical outputs for advanced CCDs  
Complete on-chip timing generator  
Precision Timing core with <600 ps resolution  
Correlated double sampler (CDS)  
6 dB to 42 dB 10-bit variable gain amplifier (VGA)  
12-bit 36 MHz ADC  
Black level clamp with variable level control  
On-chip 3 V horizontal and RG drivers  
2-phase and 4-phase H-clock modes  
The on-chip V-driver supports up to 10 channels for use with  
3-field (6-phase) CCDs. Two additional vertical outputs can be  
used with CCDs that contain advanced video readout modes.  
Voltage levels of up to +15 V and −8 V are supported.  
Electronic and mechanical shutter support  
On-chip driver for external crystal  
On-chip sync generator with external sync input  
8 mm × 8 mm CSPBGA package with 0.65 mm pitch  
The analog front end includes black level clamping, CDS, VGA,  
and a 12-bit ADC. The timing generator and V-driver provide  
all the necessary CCD clocks: RG, H-clocks, vertical clocks,  
sensor gate pulses, substrate clock, and substrate bias control.  
The internal registers are programmed using a 3-wire serial  
interface.  
APPLICATIONS  
Digital still cameras  
Digital video camcorders  
CCD camera modules  
Packaged in an 8 mm × 8 mm CSPBGA, the AD9925 is speci-  
fied over an operating temperature range of −25°C to +85°C.  
FUNCTIONAL BLOCK DIAGRAM  
REFT REFB  
AD9925  
6dB TO 42dB  
VGA  
0dB, –2dB, –4dB  
CDS  
VREF  
12  
12-BIT  
ADC  
CCDIN  
DOUT  
DCLK  
CLAMP  
INTERNAL CLOCKS  
RG  
PRECISION  
TIMING  
GENERATOR  
HORIZONTAL  
DRIVERS  
MSHUT  
4
H1 TO H4  
STROBE  
XV1 TO XV8  
8
SL  
V1, V2  
V3A, V3B  
V4, V6  
V5A, V5B  
V7, V8  
INTERNAL  
REGISTERS  
10  
SDI  
SCK  
XSG1 TO XSG6  
6
VERTICAL  
TIMING  
CONTROL  
V-DRIVER  
SYNC  
GENERATOR  
SUBCK  
RSTB  
SUBCK  
VSUB  
HD  
VD SYNC CLI CLO  
Figure 1.  
Rev. A  
Information furnished by Analog Devices is believed to be accurate and reliable.  
However, no responsibility is assumed by Analog Devices for its use, nor for any  
infringements of patents or other rights of third parties that may result from its use.  
Specifications subject to change without notice. No license is granted by implication  
or otherwise under any patent or patent rights of Analog Devices. Trademarks and  
registered trademarks are the property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Fax: 781.326.8703  
www.analog.com  
© 2004 Analog Devices, Inc. All rights reserved.  

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