AD9920A

更新时间： 2024-02-04 13:59:34

品牌	Logo	应用领域
亚德诺 - ADI		驱动器
页数	文件大小	规格书
2页	62K
描述
12-Bit CCD Signal Processor with V-Driver and Precision Timing Generator

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AD9920A 技术参数

是否无铅：	含铅	是否Rohs认证：	符合
生命周期：	Not Recommended	零件包装代码：	BGA
包装说明：	LFBGA,	针数：	105
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.1
Is Samacsys：	N	商用集成电路类型：	CONSUMER CIRCUIT
JESD-30 代码：	S-PBGA-B105	JESD-609代码：	e3
长度：	8 mm	湿度敏感等级：	1
功能数量：	1	端子数量：	105
最高工作温度：	85 °C	最低工作温度：	-25 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	LFBGA
封装形状：	SQUARE	封装形式：	GRID ARRAY, LOW PROFILE, FINE PITCH
峰值回流温度（摄氏度）：	260	认证状态：	Not Qualified
座面最大高度：	1.4 mm	最大供电电压 (Vsup)：	2 V
最小供电电压 (Vsup)：	1.6 V	表面贴装：	YES
温度等级：	OTHER	端子面层：	Matte Tin (Sn)
端子形式：	BALL	端子节距：	0.65 mm
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	30
宽度：	8 mm	Base Number Matches：	1

AD9920A 数据手册

12-Bit CCD Signal Processor with V-Driver

and Precision Timing Generator

AD9920A

FEATURES

GENERAL DESCRIPTION

Integrated 19-channel V-driver

1.8 V AFETG core

24 programmable vertical clock signals

The AD9920A is a highly integrated charge-coupled device (CCD)

signal processor for digital still camera applications. It includes a

complete analog front end (AFE) with analog-to-digital conversion,

Correlated double sampler (CDS) with −3 dB, 0 dB,

+3 dB, and +6 dB gain

12-bit, 40.5 MHz analog-to-digital converter (ADC)

Black level clamp with variable level control

Complete on-chip timing generator

Precision Timing core with ~400 ps resolution

On-chip 3 V horizontal and RG drivers

General-purpose outputs (GPOs) for shutter and

system support

On-chip sync generator with external sync input

On-chip 1.8 V low dropout (LDO)

combined with a full-function programmable timing generator

and 19-channel vertical driver (V-driver). The timing generator

is capable of supporting up to 26 vertical clock signals to control

advanced CCDs. The on-chip V-driver supports up to 19 channels

for use with 6-field CCDs. A Precision Timing™ core allows adjust-

ment of high speed clocks with approximately 400 ps resolution

at 40.5 MHz operation. The AD9920A also contains six GPOs

that can be used for shutter and system functions.

The analog front end includes black level clamping, variable

gain CDS, and a 12-bit ADC. The timing generator provides all

the necessary CCD clocks: RG, H-clocks, V-clocks, sensor gate

pulses, substrate clock, and substrate bias control.

105-lead 8 mm × 8 mm CSP_BGA package

APPLICATIONS

The AD9920A is specified over an operating temperature range

of −25°C to +85°C.

Digital still cameras

FUNCTIONAL BLOCK DIAGRAM

REFT REFB

AD9920A

–3dB, 0dB, +3dB, +6dB

VREF

12-BIT

ADC

CDS

VGA

CCDIN

DOUT

DCLK

6dB TO 42dB

CLAMP

3V INPUT

LDO

REG

1.8V OUTPUT

INTERNAL CLOCKS

PRECISION

TIMING

GENERATOR

HORIZONTAL

DRIVERS

INTERNAL

REGISTERS

SCK

H1 TO H8

XV1 TO XV24

SDATA

V1A TO V6 (3-LEVEL)

V7 TO V15 (2-LEVEL)

VERTICAL

GPO5

GPO6

VERTICAL

DRIVER

TIMING

SYNC

GENERATOR

CONTROL

SUBCK

XSUBCK

XSUBCNT

GPO1 TO GPO4,

GPO7, GPO8

CLI CLO SYNC/RSTB

Figure 1.

For more information about the AD9920A, contact Analog Devices via email at afe.ccd@analog.com.

Rev. Sp0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

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