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AD9887KS-100 PDF预览

AD9887KS-100

更新时间: 2024-02-07 17:54:40
品牌 Logo 应用领域
亚德诺 - ADI 显示器消费电路商用集成电路
页数 文件大小 规格书
40页 317K
描述
Dual Interface for Flat Panel Displays

AD9887KS-100 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QFP包装说明:PLASTIC, MQFP-160
针数:160Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.22Is Samacsys:N
商用集成电路类型:CONSUMER CIRCUITJESD-30 代码:S-PQFP-G160
JESD-609代码:e0长度:28 mm
湿度敏感等级:3功能数量:1
端子数量:160最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:QFP封装形状:SQUARE
封装形式:FLATPACK峰值回流温度(摄氏度):240
认证状态:Not Qualified座面最大高度:4.07 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn85Pb15)
端子形式:GULL WING端子节距:0.65 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:28 mmBase Number Matches:1

AD9887KS-100 数据手册

 浏览型号AD9887KS-100的Datasheet PDF文件第2页浏览型号AD9887KS-100的Datasheet PDF文件第3页浏览型号AD9887KS-100的Datasheet PDF文件第4页浏览型号AD9887KS-100的Datasheet PDF文件第5页浏览型号AD9887KS-100的Datasheet PDF文件第6页浏览型号AD9887KS-100的Datasheet PDF文件第7页 
Dual Interface for  
Flat Panel Displays  
a
AD9887  
FEATURES  
FUNCTIONAL BLOCK DIAGRAM  
Analog Interface  
140 MSPS Maximum Conversion Rate  
330 MHz Analog Bandwidth  
0.5 V to 1.0 V Analog Input Range  
500 ps p-p PLL Clock Jitter at 140 MSPS  
3.3 V Power Supply  
Full Sync Processing  
Midscale Clamp  
ANALOG  
INTERFACE  
REF  
REFOUT  
REFIN  
R
OUTA  
8
8
8
8
8
R
CLAMP  
A/D  
A/D  
A/D  
AIN  
R
OUTB  
G
OUTA  
8
8
4:2:2 Output Format Mode  
G
AIN  
CLAMP  
CLAMP  
G
OUTB  
Digital (DVI 1.0 Compatible) Interface  
112 MHz Operation (1 Pixel/Clock Mode)  
High Skew Tolerance of One Full Input Clock  
Sync Detect for Hot Plugging”  
B
8
8
OUTA  
B
B
AIN  
OUTB  
DATACK  
HSOUT  
2
APPLICATIONS  
HSYNC  
VSYNC  
COAST  
CLAMP  
CKINV  
CKEXT  
FILT  
RGB Graphics Processing  
LCD Monitors and Projectors  
Plasma Display Panels  
Scan Converters  
SYNC  
8
VSOUT  
PROCESSING  
AND CLOCK  
GENERATION  
R
OUTA  
SOGOUT  
8
8
8
8
8
2
R
OUTB  
S
CDT  
G
OUTA  
Micro Displays  
M
U
X
E
S
Digital TV  
G
OUTB  
SCL  
SDA  
B
OUTA  
SERIAL REGISTER  
AND  
B
OUTB  
A
A
1
0
POWER MANAGEMENT  
GENERAL DESCRIPTION  
DATACK  
HSOUT  
VSOUT  
SOGOUT  
DE  
The AD9887 offers designers the flexibility of a dual analog and  
digital interface for flat panel displays (FPDs) on a single chip.  
Both interfaces are optimized for excellent image quality supporting  
display resolutions up to SXGA (1280 × 1024 at 75 Hz). Either the  
analog or the digital interface can be selected by the user.  
DIGITAL  
INTERFACE  
R
8
8
OUTA  
8
8
R
OUTB  
Rx0+  
Rx0–  
Rx1+  
Rx1–  
Rx2+  
Rx2–  
RxC+  
RxC–  
G
8
8
OUTA  
Analog Interface  
G
For ease of design and to minimize cost, the AD9887 is a fully  
integrated interface solution for FPDs. The AD9887 includes an  
analog interface with a 140 MHz triple ADC with internal 1.25 V  
reference, PLL to generate a pixel clock from HSYNC, program-  
mable gain, offset, and clamp control. The user provides only a  
3.3 V power supply, analog input, and HSYNC. Three-state  
CMOS outputs may be powered from 2.5 V to 3.3 V.  
OUTB  
B
DVI  
RECEIVER  
8
8
OUTA  
8
B
OUTB  
2
DATACK  
DE  
HSYNC  
VSYNC  
R
TERM  
The AD9887’s on-chip PLL generates a pixel clock from HSYNC.  
Pixel clock output frequencies range from 12 MHz to 140 MHz.  
PLL clock jitter is 500 ps p-p typical at 140 MSPS. When a  
COAST signal is presented, the PLL maintains its output fre-  
quency in the absence of HSYNC. A sampling phase adjustment is  
provided. Data, HSYNC and Clock output phase relationships are  
maintained. The PLL can be disabled and an external clock input  
provided as the pixel clock. The AD9887 also offers full sync pro-  
cessing for composite sync and sync-on-green applications.  
AD9887  
Digital Interface  
The AD9887 contains a Digital Video Interface (DVI 1.0) compat-  
ible receiver. This receiver supports displays ranging from VGA  
to SXGA (25 MHz to 112 MHz). The receiver operates with  
true color (24-bit) panels in 1 or 2 pixel(s)/clock mode, and also  
features an intrapair skew tolerance up to one full clock cycle.  
A clamp signal is generated internally or may be provided by  
the user through the CLAMP input pin. The analog interface  
is fully programmable via a 2-wire serial interface.  
Fabricated in an advanced CMOS process, the AD9887 is pro-  
vided in a 160-lead MQFP surface mount plastic package and is  
specified over the 0°C to 70°C temperature range.  
REV. 0  
Information furnished by Analog Devices is believed to be accurate and  
reliable. However, no responsibility is assumed by Analog Devices for its  
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat  
may result from its use. No license is granted by implication or otherwise  
under any patent or patent rights of Analog Devices.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781/329-4700  
Fax: 781/326-8703  
www.analog.com  
© Analog Devices, Inc., 2001  

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