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AD9887AKS-140 PDF预览

AD9887AKS-140

更新时间： 2024-02-02 18:04:12
品牌 Logo 应用领域
亚德诺 - ADI 显示器消费电路商用集成电路
页数 文件大小 规格书
44页 380K
描述
Dual Interface for Flat Panel Displays

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AD9887AKS-140 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Active零件包装代码：QFP
包装说明：QFP,针数：160
Reach Compliance Code：unknown风险等级：5.06
Is Samacsys：N商用集成电路类型：CONSUMER CIRCUIT
JESD-30 代码：S-PQFP-G160JESD-609代码：e0
长度：28 mm湿度敏感等级：3
功能数量：1端子数量：160
最高工作温度：70 °C最低工作温度：
封装主体材料：PLASTIC/EPOXY封装代码：QFP
封装形状：SQUARE封装形式：FLATPACK
峰值回流温度（摄氏度）：240认证状态：COMMERCIAL
座面最大高度：4.1 mm最大供电电压 (Vsup)：3.45 V
最小供电电压 (Vsup)：2.2 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：TIN LEAD端子形式：GULL WING
端子节距：0.65 mm端子位置：QUAD
处于峰值回流温度下的最长时间：30宽度：28 mm
Base Number Matches：1

AD9887AKS-140 数据手册

 浏览型号AD9887AKS-140的Datasheet PDF文件第2页浏览型号AD9887AKS-140的Datasheet PDF文件第3页浏览型号AD9887AKS-140的Datasheet PDF文件第4页浏览型号AD9887AKS-140的Datasheet PDF文件第5页浏览型号AD9887AKS-140的Datasheet PDF文件第6页浏览型号AD9887AKS-140的Datasheet PDF文件第7页 
Dual Interface for  
Flat Panel Displays  
AD9887A  
FEATURES  
FUNCTIONAL BLOCK DIAGRAM  
Analog Interface  
170 MSPS Maximum Conversion Rate  
Programmable Analog Bandwidth  
0.5 V to 1.0 V Analog Input Range  
500 ps p-p PLL Clock Jitter at 170 MSPS  
3.3 V Power Supply  
Full Sync Processing  
Midscale Clamping  
4:2:2 Output Format Mode  
ANALOG INTERFACE  
REF  
REFOUT  
REFIN  
R
OUTA  
8
8
8
8
8
R
CLAMP  
CLAMP  
CLAMP  
A/D  
A/D  
A/D  
AIN  
R
OUTB  
G
OUTA  
8
8
G
AIN  
G
OUTB  
B
8
8
OUTA  
B
B
AIN  
OUTB  
Digital Interface  
DVI 1.0 Compatible Interface  
DATACK  
HSOUT  
2
HSYNC  
VSYNC  
COAST  
CLAMP  
CKINV  
CKEXT  
FILT  
170 MHz Operation (2 Pixel/Clock Mode)  
High Skew Tolerance of 1 Full Input Clock  
Sync Detect for “Hot Plugging”  
SYNC  
VSOUT  
PROCESSING  
AND CLOCK  
GENERATION  
8
SOGOUT  
R
OUTA  
Supports High Bandwidth Digital Content Protection  
S
8
8
8
8
8
2
CDT  
R
OUTB  
SOGIN  
G
APPLICATIONS  
OUTA  
SCL  
SDA  
RGB Graphics Processing  
LCD Monitors and Projectors  
Plasma Display Panels  
Scan Converters  
Micro Displays  
Digital TVs  
M
U
X
E
S
G
OUTB  
SERIAL REGISTER  
AND  
B
A
A
OUTA  
1
0
POWER MANAGEMENT  
B
OUTB  
DATACK  
R
DIGITAL INTERFACE  
8
8
8
8
OUTA  
HSOUT  
VSOUT  
SOGOUT  
8
8
8
R
OUTB  
Rx0+  
Rx0–  
Rx1+  
Rx1–  
Rx2+  
G
OUTA  
GENERAL DESCRIPTION  
G
OUTB  
The AD9887A offers designers the flexibility of an analog interface  
and digital visual interface (DVI) receiver integrated on a single  
chip. Also included is support for High Bandwidth Digital Content  
Protection (HDCP). The AD9887A is software and pin-to-pin  
compatible with the AD9887.  
DE  
B
8
8
OUTA  
Rx2–  
RxC+  
RxC–  
B
DVI  
OUTB  
RECEIVER  
2
DATACK  
DE  
R
TERM  
HSOUT  
VSOUT  
Analog Interface  
The AD9887A is a complete 8-bit 170 MSPS monolithic analog  
interface optimized for capturing RGB graphics signals from  
personal computers and workstations. Its 170 MSPS encode  
rate capability and full-power analog bandwidth of 330 MHz  
supports resolutions up to UXGA (1600 × 1200 at 60 Hz).  
DDCSCL  
DDCSDA  
MCL  
HDCP  
AD9887A  
MDA  
The analog interface includes a 170 MHz triple ADC with  
internal 1.25 V reference, a phase-locked loop (PLL), and pro-  
grammable gain, offset, and clamp control. The user provides  
only a 3.3 V power supply, analog input, and HSYNC. Three-  
state CMOS outputs may be powered from 2.5 V to 3.3 V.  
Digital Interface  
The AD9887A contains a DVI 1.0 compatible receiver and  
supports display resolutions up to UXGA (1600 ϫ 1200 at 60 Hz).  
The receiver operates with true color (24-bit) panels in 1 or  
2 pixel(s)/clock mode and features an intrapair skew tolerance  
of up to one full clock cycle.  
The AD9887A’s on-chip PLL generates a pixel clock from  
HSYNC. Pixel clock output frequencies range from 12 MHz to  
170 MHz. PLL clock jitter is typically 500 ps p-p at 170 MSPS.  
The AD9887A also offers full sync processing for composite  
sync and sync-on-green (SOG) applications.  
With the inclusion of HDCP, displays may now receive encrypted  
video content. The AD9887A allows for authentication of a  
video receiver, decryption of encoded data at the receiver, and  
renewability of that authentication during transmission as specified  
by the HDCP v1.0 protocol.  
Fabricated in an advanced CMOS process, the AD9887A is  
provided in a 160-lead MQFP surface-mount plastic package  
and is specified over the 0°C to 70°C temperature range.  
REV. 0  
Information furnished by Analog Devices is believed to be accurate and  
reliable. However, no responsibility is assumed by Analog Devices for its  
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat  
may result from its use. No license is granted by implication or otherwise  
under any patent or patent rights of Analog Devices. Trademarks and  
registered trademarks are the property of their respective companies.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781/329-4700  
Fax: 781/326-8703  
www.analog.com  
© 2003 Analog Devices, Inc. All rights reserved.  
 
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