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AD9882AKSTZ-100 PDF预览

AD9882AKSTZ-100

更新时间: 2024-01-01 00:07:23
品牌 Logo 应用领域
亚德诺 - ADI 显示器消费电路商用集成电路输出元件PC
页数 文件大小 规格书
40页 1484K
描述
Dual Interface for Flat Panel Displays

AD9882AKSTZ-100 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:QFP
包装说明:LFQFP,针数:100
Reach Compliance Code:unknown风险等级:5.05
Is Samacsys:N其他特性:IT ALSO REQUIRES 2.2V TO 3.6V FOR OUTPUT
商用集成电路类型:CONSUMER CIRCUITJESD-30 代码:S-PQFP-G100
JESD-609代码:e3长度:14 mm
湿度敏感等级:3功能数量:1
端子数量:100最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:LFQFP封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE, FINE PITCH峰值回流温度(摄氏度):260
认证状态:COMMERCIAL座面最大高度:1.6 mm
最大供电电压 (Vsup):3.45 V最小供电电压 (Vsup):3.15 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:MATTE TIN
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:40
宽度:14 mmBase Number Matches:1

AD9882AKSTZ-100 数据手册

 浏览型号AD9882AKSTZ-100的Datasheet PDF文件第2页浏览型号AD9882AKSTZ-100的Datasheet PDF文件第3页浏览型号AD9882AKSTZ-100的Datasheet PDF文件第4页浏览型号AD9882AKSTZ-100的Datasheet PDF文件第5页浏览型号AD9882AKSTZ-100的Datasheet PDF文件第6页浏览型号AD9882AKSTZ-100的Datasheet PDF文件第7页 
Dual Interface for  
Flat Panel Displays  
AD9882A  
FUNCTIONAL BLOCK DIAGRAM  
FEATURES  
Analog interface  
AD9882A  
ANALOG INTERFACE  
CLAMP  
REF  
REFBYPASS  
140 MSPS maximum conversion rate  
Programmable analog bandwidth  
0.5 V to 1.0 V analog input range  
500 ps p-p PLL clock jitter at 140 MSPS  
3.3 V power supply  
Full sync processing  
Midscale clamping  
4:2:2 output format mode  
Digital interface  
R
8
8
8
OUT  
R
G
B
A/D  
A/D  
A/D  
AIN  
AIN  
AIN  
G
B
OUT  
CLAMP  
CLAMP  
OUT  
8
8
8
DATACK  
HSOUT  
R
OUT  
SOGIN  
HSYNC  
SYNC  
PROCESSING AND  
CLOCK  
VSOUT  
G
OUT  
FILT  
VSYNC  
GENERATION  
SOGOUT  
B
OUT  
DVI 1.0 compatible interface  
112 MHz operation  
High skew tolerance of 1 full input clock  
Sync detect for hot plugging  
Supports high bandwidth digital content protection  
SCL  
SDA  
DATACK  
HSOUT  
SERIAL REGISTER AND  
POWER MANAGEMENT  
A
0
CSOUT  
DIGITAL INTERFACE  
8
R
R
R
R
R
X0+  
X0–  
X1+  
X1–  
X2+  
R
SOGOUT  
OUT  
G
8
OUT  
DE  
DVI  
RECEIVER  
APPLICATIONS  
RGB graphics processing  
LCD monitors and projectors  
Plasma display panels  
Scan converter  
B
8
OUT  
R
X2–  
XC+  
XC–  
DATACK  
DE  
R
R
R
TERM  
DDCSCL  
DDCSDA  
MCL  
HSYNC  
VSYNC  
HDCP  
Microdisplays  
MDA  
Digital TV  
Figure 1.  
GENERAL DESCRIPTION  
The AD9882A also offers full sync processing for composite  
sync and sync-on-green (SOG) applications.  
The AD9882A offers designers the flexibility of an analog inter-  
face and a digital visual interface (DVI) receiver integrated on a  
single chip. Also included is support for high bandwidth digital  
content protection (HDCP).  
Digital Interface  
The AD9882A contains a DVI 1.0 compatible receiver and  
supports display resolutions up to SXGA (1280 × 1024 at  
60 Hz). The receiver features an intrapair skew tolerance of up  
to one full clock cycle.  
Analog Interface  
The AD9882A is a complete, 8-bit, 140 MSPS monolithic  
analog interface optimized for capturing RGB graphics signals  
from personal computers and workstations. Its 140 MSPS  
encode rate capability and full power analog bandwidth of 300  
MHz sup-ports resolutions up to SXGA (1280 × 1024 at 75 Hz).  
With the inclusion of HDCP, displays can now receive  
encrypted video content. The AD9882A allows for authentica-  
tion of a video receiver, decryption of encoded data at the  
receiver, and renewability of that authentication during trans-  
mission, as specified by the HDCP v1.0 protocol. It also has  
high tolerance of noncompliant HDCP sources.  
The analog interface includes a 140 MHz triple ADC with  
internal 1.25 V reference, a phase-locked loop (PLL), program-  
mable gain, offset, and clamp control. The user provides only a  
3.3 V power supply, analog input, and Hsync. Three-state  
CMOS outputs can be powered from 2.2 V to 3.3 V.  
Fabricated in an advanced CMOS process, the AD9882A is  
provided in a space-saving, 100-lead LQFP surface-mount  
plastic package and is specified over the 0°C to 70°C  
temperature range. It is available in a Pb-free package.  
The AD9882A’s on-chip PLL generates a pixel clock from  
Hsync. Pixel clock output frequencies range from 12 MHz to  
140 MHz. PLL clock jitter is typically 500 ps p-p at 140 MSPS.  
Rev. 0  
Information furnished by Analog Devices is believed to be accurate and reliable.  
However, no responsibility is assumed by Analog Devices for its use, nor for any  
infringements of patents or other rights of third parties that may result from its use.  
Specifications subject to change without notice. No license is granted by implication  
or otherwise under any patent or patent rights of Analog Devices. Trademarks and  
registered trademarks are the property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Fax: 781.326.8703  
www.analog.com  
© 2004 Analog Devices, Inc. All rights reserved.  
 
 

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