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AD9878BSTZ PDF预览

AD9878BSTZ

更新时间: 2024-02-15 12:35:05
品牌 Logo 应用领域
亚德诺 - ADI 电信集成电路电信电路
页数 文件大小 规格书
36页 749K
描述
Mixed-Signal Front End for Broadband Applications

AD9878BSTZ 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:QFP
包装说明:LFQFP,针数:100
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.67JESD-30 代码:S-PQFP-G100
JESD-609代码:e3长度:14 mm
功能数量:1端子数量:100
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE, FINE PITCH
峰值回流温度(摄氏度):NOT SPECIFIED认证状态:Not Qualified
座面最大高度:1.6 mm标称供电电压:3.3 V
表面贴装:YES电信集成电路类型:TELECOM CIRCUIT
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:14 mmBase Number Matches:1

AD9878BSTZ 数据手册

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Mixed-Signal Front End  
for Broadband Applications  
AD9878  
FUNCTIONAL BLOCK DIAGRAM  
FEATURES  
Low cost 3.3 V CMOS MxFE™ for broadband applications  
DOCSIS, EURO-DOCSIS, DVB, DAVIC compliant  
232 MHz quadrature digital upconverter  
12-bit direct IF DAC (TxDAC+®)  
I
12  
–1  
16  
SINC  
Tx  
DAC  
TxID[5:0]  
Q
Tx  
DDS  
Σ-∆  
Σ-OUTPUT  
Up to 65 MHz carrier frequency DDS  
Programmable sampling clock rates  
Analog Tx output level adjust  
3
4
CA PORT  
MCLK  
SDIO  
CONTROL REGISTERS  
PLL  
OSCIN  
Dual 12-bit, 29 MSPS direct IF ADCs with video clamp input  
10-bit, 29 MSPS sampling ADC  
8-bit ∑-∆ auxiliary DAC  
10  
IF10[4:0]  
IF10 INPUT  
ADC  
MUX  
MUX  
12  
IF12B INPUT  
VIDEO IN  
ADC  
MUX  
Direct interface to AD832x family of PGA cable drivers  
Σ
APPLICATIONS  
IF12[11:0]  
FLAG[2:1]  
CLAMP  
LEVEL  
Cable set-top boxes  
Cable and wireless modems  
MUX  
12  
IF12A INPUT  
ADC  
Figure 1.  
GENERAL DESCRIPTION  
The AD9878 is a single-supply, cable modem/set-top box,  
mixed-signal front end. The device contains a transmit path  
interpolation filter, a complete quadrature digital upconverter,  
and a transmit DAC. The receive path contains dual 12-bit  
ADCs and a 10-bit ADC. All internally required clocks and an  
output system clock are generated by the phase-locked loop  
(PLL) from a single crystal oscillator or clock input.  
The 12-bit ADCs provide excellent undersampling performance,  
allowing this device to typically deliver better than 10 ENOBs  
with IF inputs up to 70 MHz. The 12-bit IF ADCs can sample at  
rates up to 29 MHz, allowing them to process wideband signals.  
The AD9878 includes a programmable ∑-∆ DAC, which can be  
used to control an external component such as a variable gain  
amplifier (VGA) or a voltage controlled tuner.  
The transmit path interpolation filter provides an upsampling  
factor of 16× with an output signal bandwidth up to 4.35 MHz.  
Carrier frequencies up to 65 MHz with 26 bits of frequency tuning  
resolution can be generated by the direct digital synthesizer  
(DDS). The transmit DAC resolution is 12 bits and can run at  
sampling rates as high as 232 MSPS. Analog output scaling from  
0 dB to 7.5 dB in 0.5 dB steps is available to preserve SNR when  
reduced output levels are required.  
The AD9878 also integrates a CA port that enables a host  
processor to interface with the AD832x family of programmable  
gain amplifier (PGA) cable drivers or industry equivalent via  
the MxFE serial port (SPORT).  
The AD9878 is available in a 100-lead, LQFP package. The  
AD9878 is specified over the extended industrial (−40°C to  
+85°C) temperature range.  
Rev. A  
Information furnished by Analog Devices is believed to be accurate and reliable.  
However, no responsibility is assumed by Analog Devices for its use, nor for any  
infringements of patents or other rights of third parties that may result from its use.  
Specifications subject to change without notice. No license is granted by implication  
or otherwise under any patent or patent rights of Analog Devices. Trademarks and  
registered trademarks are the property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Fax: 781.326.8703  
www.analog.com  
© 2005 Analog Devices, Inc. All rights reserved.  

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