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AD9877 PDF预览

AD9877

更新时间: 2024-01-08 09:28:57
品牌 Logo 应用领域
亚德诺 - ADI 调制解调器电缆调制解调器
页数 文件大小 规格书
36页 523K
描述
Mixed-Signal Front End Set-Top Box, Cable Modem

AD9877 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QFP包装说明:METRIC, QFP-100
针数:100Reach Compliance Code:compliant
ECCN代码:5A991.GHTS代码:8542.39.00.01
风险等级:5.84JESD-30 代码:R-PQFP-G100
JESD-609代码:e0长度:20 mm
功能数量:1端子数量:100
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:QFP
封装形状:RECTANGULAR封装形式:FLATPACK
峰值回流温度(摄氏度):220认证状态:Not Qualified
座面最大高度:3.4 mm标称供电电压:3.3 V
表面贴装:YES技术:CMOS
电信集成电路类型:TELECOM CIRCUIT温度等级:INDUSTRIAL
端子面层:TIN LEAD端子形式:GULL WING
端子节距:0.65 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:14 mm

AD9877 数据手册

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Mixed-Signal Front End  
Set-Top Box, Cable Modem  
AD9877  
FUNCTIONAL BLOCK DIAGRAM  
FEATURES  
Low cost 3.3 V CMOS MxFE™ for  
COS  
MCNS-DOCSIS-, DVB-, DAVIC-compliant  
set-top box and cable modem applications  
232 MHz quadrature digital upconverter  
12-bit direct IF DAC (TxDAC+®)  
Up to 65 MHz carrier frequency DDS  
Programmable sampling clock rates  
Selectable interpolation filter  
Analog Tx output level adjust  
12-bit, 33 MSPS direct IF ADC  
Dual 8-bit, 16.5 MSPS sampling IQ ADCs  
Two 12-bit Σ-Δ auxiliary DACs  
INTER-  
POLATOR  
FILTER  
12  
Tx  
DAC  
Tx DATA  
Tx  
3
CA  
SIN  
DDS  
12  
12  
PLL  
SDELTA0  
Σ-Δ  
Σ-Δ  
4
SPORT  
PROFILE  
CONTROL FUNCTIONS  
8
SDELTA1  
REFCLK  
2
I IN  
ADC  
ADC  
ADC  
RxIQ DATA  
RxIF DATA  
Rx  
8
Q IN  
IF IN  
12  
AD9877  
Direct interface to AD8321/AD8325 or  
AD8322/AD8327 PGA cable driver  
Figure 1.  
APPLICATIONS  
Cable modems  
Set-top boxes  
Wireless modems  
GENERAL DESCRIPTION  
The AD9877 is a single-supply set-top box and cable modem  
mixed-signal front end. The device contains a transmit path  
interpolation filter, complete quadrature digital upconverter,  
and transmit DAC. The receive path contains a 12-bit ADC and  
dual 8-bit ADCs. All internally required clocks and an output  
system clock are generated by the phase-locked loop (PLL) from  
a single crystal or clock input.  
The 12-bit ADC has excellent undersampling performance,  
allowing it to typically deliver better than 10 ENOBs with IF  
inputs up to 70 MHz. The 12-bit IF ADC can sample at a rate  
up to 33 MHz, allowing it to process wideband signal inputs.  
Two programmable Σ-Δ DACs are available and can be used to  
control external components, such as variable gain amplifiers  
(VGAs) or voltage-controlled tuners.  
The transmit path interpolation filter provides upsampling  
factors of 12× or 16× with an output signal bandwidth as high  
as 5.8 MHz. Carrier frequencies up to 65 MHz with 26 bits of  
frequency tuning resolution can be generated by the direct  
digital synthesizer (DDS). The transmit DAC resolution is 12 bits  
and can run at sampling rates as high as 232 MSPS. Analog  
output scaling from 0 dB to 7.5 dB in 0.5 dB steps is available to  
preserve SNR when reduced output levels are required.  
The AD9877 integrates a CA port that enables a host processor  
to control the AD8321/AD8325 or AD8322/AD8327  
programmable gain amplifier (PGA) cable drivers via the  
MxFE SPORT.  
The AD9877 is available in a 100-lead MQFP package. It offers  
enhanced receive path undersampling performance and lower  
cost compared to the pin-compatible AD9873. The AD9877 is  
specified over the extended industrial (−40°C to +85°C)  
temperature range.  
Rev. B  
Information furnished by Analog Devices is believed to be accurate and reliable.  
However, no responsibility is assumed by Analog Devices for its use, nor for any  
infringements of patents or other rights of third parties that may result from its use.  
Specifications subject to change without notice. No license is granted by implication  
or otherwise under any patent or patent rights of Analog Devices. Trademarks and  
registered trademarks are the property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Fax: 781.461.3113  
www.analog.com  
© 2005 Analog Devices, Inc. All rights reserved.  

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