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AD9874 PDF预览

AD9874

更新时间: 2024-02-03 17:25:33
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
40页 730K
描述
IF Digitizing Subsystem

AD9874 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:QFP
包装说明:LFQFP,针数:48
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.62JESD-30 代码:S-PQFP-G48
JESD-609代码:e3长度:7 mm
功能数量:1端子数量:48
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE, FINE PITCH
峰值回流温度(摄氏度):NOT SPECIFIED认证状态:Not Qualified
座面最大高度:1.6 mm标称供电电压:3 V
表面贴装:YES电信集成电路类型:TELECOM CIRCUIT
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7 mmBase Number Matches:1

AD9874 数据手册

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a
IF Digitizing Subsystem  
AD9874*  
FEATURES  
GENERAL DESCRIPTION  
10 MHz–300 MHz Input Frequency  
6.8 kHz–270 kHz Output Signal Bandwidth  
8.1 dB SSB NF  
The AD9874 is a general-purpose IF subsystem that digitizes a  
low level 10 MHz–300 MHz IF input with a signal bandwidth  
ranging from 6.8 kHz to 270 kHz. The signal chain of the AD9874  
consists of a low noise amplifier, a mixer, a band-pass sigma-delta  
analog-to-digital converter, and a decimation filter with program-  
mable decimation factor. An automatic gain control (AGC) circuit  
gives the AD9874 12 dB of continuous gain adjustment. Auxiliary  
blocks include both clock and LO synthesizers.  
0 dBm IIP3  
AGC Free Range up to –34 dBm  
12 dB Continuous AGC Range  
16 dB Front End Attenuator  
Baseband I/Q 16-bit (or 24-bit) Serial Digital Output  
LO and Sampling Clock Synthesizers  
Programmable Decimation Factor, Output Format,  
AGC, and Synthesizer Settings  
370 Input Impedance  
The AD9874’s high dynamic range and inherent antialiasing  
provided by the band-pass sigma-delta converter allow the  
AD9874 to cope with blocking signals up to 95 dB stronger  
than the desired signal. This attribute can often reduce the cost of  
2.7 V–3.6 V Supply Voltage  
Low Current Consumption: 20 mA  
48–Lead LQFP Package (1.4 mm Thick)  
a
radio by reducing its IF filtering requirements. Also, it enables  
multimode radios of varying channel bandwidths, allowing the  
IF filter to be specified for the largest channel bandwidth.  
APPLICATIONS  
The SPI port programs numerous parameters of the AD9874,  
thus allowing the device to be optimized for any given  
application. Programmable parameters include the following:  
synthesizer divide ratios; AGC attenuation and attack/decay  
time; the received signal strength level; decimation factor; the  
output data format; 16 dB attenuator; and the selected bias  
currents. The bias currents of the LNA and mixer can be further  
reduced at the expense of the degraded performance for battery-  
powered applications.  
Multimode Narrowband Radio Products  
Analog/Digital UHF/VHF FDMA Receivers  
TETRA, APCO25, GSM/EDGE  
Portable and Mobile Radio Products  
Base Station Applications  
FUNCTIONAL BLOCK DIAGRAM  
MXOP MXON IF2P IF2N  
GCP GCN  
DAC  
AGC  
AD9874  
–16dB  
LNA  
DECIMATION  
FILTER  
IFIN  
-ADC  
FORMATTING/SSI  
DOUTA  
DOUTB  
FS  
CLKOUT  
FREF  
CONTROL LOGIC  
LO  
SYNC  
SAMPLE CLOCK  
SYNTHESIZER  
VOLTAGE  
REFERENCE  
SPI  
IOUTL  
LOP LON  
IOUTC CLKP  
CLKN VREFP VCM VREFN PC PD PE  
SYNCB  
LO VCO AND  
LOOP FILTER  
LO VCO AND  
LOOP FILTER  
*Protected by U.S. Patent No. 5,969,657; other patents pending.  
REV. 0  
Information furnished by Analog Devices is believed to be accurate and  
reliable. However, no responsibility is assumed by Analog Devices for its  
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat  
may result from its use. No license is granted by implication or otherwise  
under any patent or patent rights of Analog Devices.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781/329-4700  
Fax: 781/326-8703  
www.analog.com  
© Analog Devices, Inc., 2002  

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