CMOS 300 MSPS Complete DDS
AD9852
Frequency ramped FSK
FEATURES
<25 ps rms total jitter in clock generator mode
Automatic bidirectional frequency sweeping
Sin(x)/x correction
300 MHz internal clock rate
FSK, BPSK, PSK, chirp, AM operation
Dual integrated 12-bit D/A converters
Ultrahigh speed comparator, 3 ps rms jitter
Excellent dynamic performance
80 dB SFDR at 100 MHz ( 1 MHz) AOUT
4× to 20× programmable reference clock multiplier
Dual 48-bit programmable frequency registers
Dual 14-bit programmable phase offset registers
12-bit programmable amplitude modulation and on/off
output shaped keying function
Simplified control interface
10 MHz serial 2-wire or 3-wire SPI-compatible
100 MHz parallel 8-bit programming
3.3 V single supply
Multiple power-down functions
Single-ended or differential input reference clock
Small, 80-lead LQFP or TQFP with exposed pad
APPLICATIONS
Single-pin FSK and BPSK data interfaces
PSK capability via I/O interface
Linear or nonlinear FM chirp functions with single pin
frequency hold function
Agile LO frequency synthesis
Programmable clock generator
FM chirp source for radar and scanning systems
Test and measurement equipment
Commercial and amateur RF exciter
FUNCTIONAL BLOCK DIAGRAM
DIGITAL MULTIPLIERS
SYSTEM CLOCK
INV
SINC
FILTER
DDS CORE
12
12
4× TO 20×
12-BIT
COSINE
DAC
ANALOG
OUT
REFERENCE
CLOCK IN
I
REFCLK
BUFFER
REFCLK
MULTIPLIER
48
48
17
17
SYSTEM
CLOCK
DAC R
SET
DIFF/SINGLE
SELECT
MUX
12-BIT
CONTROL
DAC
ANALOG
OUT
SYSTEM
CLOCK
14
48
Q
12
3
FSK/BPSK/HOLD
DATA IN
MUX
48
MUX
MUX
ANALOG
IN
DELTA
FREQUENCY
RATE TIMER
PROGRAMMABLE
AMPLITUDE AND
RATE CONTROL
SYSTEM
CLOCK
2
48
48
14
COMPARATOR
12
SYSTEM
CLOCK
14
CLOCK
OUT
DELTA
FREQUENCY
WORD
FREQUENCY FREQUENCY
FIRST 14-BIT
PHASE/OFFSET
WORD
SECOND 14-BIT
PHASE/OFFSET MODULATION CONTROL
WORD
AM
12-BIT DC
TUNING
WORD 1
TUNING
WORD 2
PROGRAMMING REGISTERS
SYSTEM
MODE SELECT
OSK
GND
SYSTEM
CLOCK
CLK
AD9852
÷2
BUS
CLOCK
Q
D
BIDIRECTIONAL
INTERNAL/EXTERNAL
I/O UPDATE CLOCK
INT
EXT
INTERNAL
PROGRAMMABLE
UPDATE CLOCK
I/O PORT BUFFERS
+V
S
READ
WRITE SERIAL/
6-BIT ADDRESS
OR SERIAL
PROGRAMMING
LINES
8-BIT
PARALLEL
LOAD
MASTER
RESET
PARALLEL
SELECT
Figure 1.
Rev. E
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