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AD9549ABCPZ-REEL7

更新时间： 2024-02-10 19:03:49

品牌	Logo	应用领域
亚德诺 - ADI		晶体时钟发生器微控制器和处理器外围集成电路 PC
页数	文件大小	规格书
76页	1905K
描述
Dual Input Network Clock Generator/Synchronizer

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技术参数
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AD9549ABCPZ-REEL7 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	QFN
包装说明：	HVQCCN,	针数：	64
Reach Compliance Code：	unknown	风险等级：	5.77
Is Samacsys：	N	JESD-30 代码：	S-XQCC-N64
JESD-609代码：	e3	长度：	9 mm
湿度敏感等级：	1	端子数量：	64
最高工作温度：	85 °C	最低工作温度：	-40 °C
最大输出时钟频率：	750 MHz	封装主体材料：	UNSPECIFIED
封装代码：	HVQCCN	封装形状：	SQUARE
封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	峰值回流温度（摄氏度）：	225
主时钟/晶体标称频率：	1000 MHz	认证状态：	COMMERCIAL
座面最大高度：	1 mm	最大供电电压：	1.89 V
最小供电电压：	1.71 V	标称供电电压：	1.8 V
表面贴装：	YES	温度等级：	INDUSTRIAL
端子面层：	MATTE TIN	端子形式：	NO LEAD
端子节距：	0.5 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	9 mm
uPs/uCs/外围集成电路类型：	CLOCK GENERATOR, OTHER	Base Number Matches：	1

AD9549ABCPZ-REEL7 数据手册

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Dual Input Network Clock

Generator/Synchronizer

AD9549

FEATURES

APPLICATIONS

Flexible reference inputs

Network synchronization

Input frequencies: 8 kHz to 750 MHz

Two reference inputs

Loss of reference indicators

Reference clock jitter cleanup

SONET/SDH clocks up to OC-192, including FEC

Stratum 3/3E reference clocks

Wireless base station, controllers

Cable infrastructure

Auto and manual holdover modes

Auto and manual switchover modes

Smooth A-to-B phase transition on outputs

Excellent stability in holdover mode

Programmable 16 + 1-bit input divider, R

Differential HSTL clock output

Data communications

GENERAL DESCRIPTION

The AD9549 provides synchronization for many systems,

including synchronous optical networks (SONET/SDH). The

AD9549 generates an output clock, synchronized to one of two

external input references. The external references may contain

significant time jitter, also specified as phase noise. Using a

digitally controlled loop and holdover circuitry, the AD9549

continues to generate a clean (low jitter), valid output clock during

a loss of reference condition, even when both references have failed.

Output frequencies to 750 MHz

Low jitter clock doubler for frequencies of >400 MHz

Single-ended CMOS output for frequencies of <150 MHz

Programmable digital loop filter (<1 Hz to ~100 kHz)

High speed digitally controlled oscillator (DCO) core

Direct digital synthesizer (DDS) with integrated 14-bit DAC

Excellent dynamic performance

Programmable 16 + 1-bit feedback divider, S

Software controlled power-down

Available 64-lead LFCSP package

The AD9549 operates over an industrial temperature range of

−40°C to +85°C.

BASIC BLOCK DIAGRAM

AD9549

S1 TO S4

FDBK_IN

FILTER

DAC_OUT

REFERENCE

MONITORS

AND

REFA_IN

REFB_IN

OUT

DIGITAL PLL

R, S DIVIDERS

HOLDOVER

CLOCK

OUTPUT

DRIVERS

OUT_CMOS

SWITCHING

SERIAL PORT,

I/O LOGIC

SYSTEM CLOCK

MULTIPLIER

DIGITAL INTERFACE

Figure 1.

Rev. D

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rightsof third parties that may result fromits use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks andregisteredtrademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700 www.analog.com

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