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AD9548

更新时间: 2024-01-26 20:04:04
品牌 Logo 应用领域
亚德诺 - ADI 时钟发生器
页数 文件大小 规格书
112页 1935K
描述
Quad/Octal Input Network Clock Generator/Synchronizer

AD9548 技术参数

是否无铅: 含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:QFN
包装说明:HVQCCN,针数:88
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:1.64
JESD-30 代码:S-XQCC-N88JESD-609代码:e3
长度:12 mm湿度敏感等级:3
端子数量:88最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:UNSPECIFIED
封装代码:HVQCCN封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):260
主时钟/晶体标称频率:1000 MHz认证状态:Not Qualified
座面最大高度:0.9 mm最大供电电压:1.89 V
最小供电电压:1.71 V标称供电电压:1.8 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:40
宽度:12 mmuPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHER
Base Number Matches:1

AD9548 数据手册

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Quad/Octal Input Network Clock  
Generator/Synchronizer  
AD9548  
FEATURES  
APPLICATIONS  
Supports Stratum 2 stability in holdover mode  
Supports reference switchover with phase build-out  
Supports hitless reference switchover  
Auto/manual holdover and reference switchover  
4 pairs of reference input pins with each pair configurable as  
a single differential input or as 2 independent single-  
ended inputs  
Input reference frequencies from 1 Hz to 750 MHz  
Reference validation and frequency monitoring (1 ppm)  
Programmable input reference switchover priority  
30-bit programmable input reference divider  
4 pairs of clock output pins with each pair configurable as a  
single differential LVDS/LVPECL output or as 2 single-  
ended CMOS outputs  
Output frequencies up to 450 MHz  
30-bit integer and 10-bit fractional programmable feedback  
divider  
Programmable digital loop filter covering loop bandwidths  
from 0.001 Hz to 100 kHz  
Optional low noise LC-VCO system clock multiplier  
Optional crystal resonator for system clock input  
On-chip EEPROM to store multiple power-up profiles  
Software controlled power-down  
Network synchronization  
Cleanup of reference clock jitter  
GPS 1 pulse per second synchronization  
SONET/SDH clocks up to OC-192, including FEC  
Stratum 2 holdover, jitter cleanup, and phase transient  
control  
Stratum 3E and Stratum 3 reference clocks  
Wireless base station controllers  
Cable infrastructure  
Data communications  
GENERAL DESCRIPTION  
The AD9548 provides synchronization for many systems,  
including synchronous optical networks (SONET/SDH). The  
AD9548 generates an output clock synchronized to one of up to  
four differential or eight single-ended external input references.  
The digital PLL allows for reduction of input time jitter or phase  
noise associated with the external references. The AD9548  
continuously generates a clean (low jitter), valid output clock  
even when all references have failed by means of a digitally  
controlled loop and holdover circuitry.  
The AD9548 operates over an industrial temperature range of  
−40°C to +85°C.  
88-lead LFCSP package  
FUNCTIONAL BLOCK DIAGRAM  
ANALOG  
FILTER  
STABLE  
SOURCE  
AD9548  
CLOCK DISTRIBUTION  
CLOCK  
MULTIPLIER  
CHANNEL 0  
DIVIDER  
CHANNEL 1  
DIVIDER  
DIGITAL  
PLL  
CHANNEL 2  
DIVIDER  
DAC  
REFERENCE INPUTS  
AND  
MONITOR MUX  
CHANNEL 3  
DIVIDER  
SYNC  
SERIAL CONTROL INTERFACE  
STATUS AND  
CONTROL PINS  
EEPROM  
2
(SPI or I C)  
Figure 1.  
Rev. 0  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rights of third parties that may result from its use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks and registeredtrademarks arethe property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Fax: 781.461.3113  
www.analog.com  
©2009 Analog Devices, Inc. All rights reserved.  
 

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