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AD9516-0BCPZ PDF预览

AD9516-0BCPZ

更新时间: 2024-01-28 01:21:47
品牌 Logo 应用领域
亚德诺 - ADI 时钟驱动器时钟发生器逻辑集成电路
页数 文件大小 规格书
84页 1918K
描述
14-Output Clock Generator with Integrated 2.8 GHz VCO

AD9516-0BCPZ 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:QFN
包装说明:HVQCCN,针数:64
Reach Compliance Code:unknown风险等级:5.68
系列:9516输入调节:DIFFERENTIAL MUX
JESD-30 代码:S-XQCC-N64JESD-609代码:e3
长度:9 mm逻辑集成电路类型:PLL BASED CLOCK DRIVER
湿度敏感等级:3功能数量:1
反相输出次数:端子数量:64
实输出次数:10最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
封装主体材料:UNSPECIFIED封装代码:HVQCCN
封装形状:SQUARE封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度):260传播延迟(tpd):2.6 ns
认证状态:COMMERCIALSame Edge Skew-Max(tskwd):0.675 ns
座面最大高度:1 mm最大供电电压 (Vsup):3.465 V
最小供电电压 (Vsup):3.135 V标称供电电压 (Vsup):3.3 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:MATTE TIN端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:40宽度:9 mm
最小 fmax:2950 MHzBase Number Matches:1

AD9516-0BCPZ 数据手册

 浏览型号AD9516-0BCPZ的Datasheet PDF文件第2页浏览型号AD9516-0BCPZ的Datasheet PDF文件第3页浏览型号AD9516-0BCPZ的Datasheet PDF文件第4页浏览型号AD9516-0BCPZ的Datasheet PDF文件第5页浏览型号AD9516-0BCPZ的Datasheet PDF文件第6页浏览型号AD9516-0BCPZ的Datasheet PDF文件第7页 
14-Output Clock Generator with  
Integrated 2.8 GHz VCO  
AD9516-0  
FUNCTIONAL BLOCK DIAGRAM  
FEATURES  
CP  
LF  
Low phase noise, phase-locked loop  
On-chip VCO tunes from 2.55 GHz to 2.95 GHz  
External VCO/VCXO to 2.4 GHz optional  
One differential or two single-ended reference inputs  
Reference monitoring capability  
Auto and manual reference switchover/holdover modes  
Autorecover from holdover  
Accepts references to 250 MHz  
Programmable delays in path to PFD  
Digital or analog lock detect, selectable  
3 pairs of 1.6 GHz LVPECL outputs  
Each pair shares 1 to 32 divider with coarse phase delay  
Additive output jitter 225 fS rms  
Channel-to-channel skew paired outputs <10 ps  
2 pairs of 800 MHz LVDS clock outputs  
Each pair shares two cascaded 1 to 32 dividers with coarse  
phase delay  
REF1  
REF2  
STATUS  
MONITOR  
REFIN  
CLK  
VCO  
DIVIDER  
AND MUXs  
OUT0  
OUT1  
OUT2  
OUT3  
OUT4  
OUT5  
OUT6  
OUT7  
OUT8  
OUT9  
DIV/Φ  
DIV/Φ  
DIV/Φ  
DIV/Φ  
DIV/Φ  
LVPECL  
LVPECL  
LVPECL  
ΔT  
ΔT  
ΔT  
ΔT  
DIV/Φ  
DIV/Φ  
LVDS/CMOS  
LVDS/CMOS  
SERIAL CONTROL PORT  
AND  
Additive output jitter 275 fS rms  
AD9516-0  
DIGITAL LOGIC  
Fine delay adjust (ΔT) on each LVDS output  
Eight 250 MHz CMOS outputs (two per LVDS output)  
Automatic synchronization of all outputs on power-up  
Manual synchronization of outputs as needed  
Serial control port  
Figure 1.  
The AD9516-0 features six LVPECL outputs (in three pairs);  
four LVDS outputs (in two pairs); and eight CMOS outputs  
(two per LVDS output). The LVPECL outputs operate to  
1.6 GHz, the LVDS outputs operate to 800 MHz, and the CMOS  
outputs operate to 250 MHz.  
64-lead LFCSP  
APPLICATIONS  
Each pair of outputs has dividers that allow both the divide  
ratio and coarse delay (or phase) to be set. The range of division  
for the LVPECL outputs is 1 to 32. The LVDS/CMOS outputs  
allow a range of divisions up to a maximum of 1024.  
Low jitter, low phase noise clock distribution  
Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs  
High performance wireless transceivers  
High performance instrumentation  
Broadband infrastructure  
The AD9516-0 is available in a 64-lead LFCSP and can be  
operated from a single 3.3 V supply. An external VCO, which  
requires an extended voltage range, can be accommodated  
by connecting the charge pump supply (VCP) to 5.5 V. A  
separate LVPECL power supply can be from 2.375 V to 3.6 V.  
ATE  
GENERAL DESCRIPTION  
The AD9516-01 provides a multi-output clock distribution  
function with subpicosecond jitter performance, along with an on-  
chip PLL and VCO. The on-chip VCO tunes from 2.55 GHz to  
2.95 GHz. Optionally, an external VCO/VCXO of up to 2.4 GHz  
may be used.  
The AD9516-0 is specified for operation over the industrial  
range of −40°C to +85°C.  
1 AD9516 is used throughout to refer to all the members of the AD9516  
family. However, when AD9516-0 is used it is referring to that specific  
member of the AD9516 family.  
The AD9516-0 emphasizes low jitter and phase noise to  
maximize data converter performance, and can benefit other  
applications with demanding phase noise and jitter requirements.  
Rev. 0  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rights of third parties that may result from its use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks and registeredtrademarks arethe property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Fax: 781.461.3113  
www.analog.com  
©2007 Analog Devices, Inc. All rights reserved.  
 

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