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AD809BR-REEL7 PDF预览

AD809BR-REEL7

更新时间: 2024-02-07 20:12:31
品牌 Logo 应用领域
亚德诺 - ADI 晶体时钟发生器微控制器和处理器外围集成电路光电二极管
页数 文件大小 规格书
8页 285K
描述
155.52 MHz Frequency Synthesizer

AD809BR-REEL7 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Active零件包装代码:SOIC
包装说明:SOP,针数:16
Reach Compliance Code:unknown风险等级:5.89
JESD-30 代码:R-PDSO-G16JESD-609代码:e0
长度:9.9 mm湿度敏感等级:1
端子数量:16最高工作温度:85 °C
最低工作温度:-40 °C最大输出时钟频率:155.52 MHz
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):240主时钟/晶体标称频率:19.44 MHz
认证状态:COMMERCIAL座面最大高度:1.75 mm
最大供电电压:5.5 V最小供电电压:4.5 V
标称供电电压:5 V表面贴装:YES
技术:ECL温度等级:INDUSTRIAL
端子面层:TIN LEAD端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:3.9 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHER

AD809BR-REEL7 数据手册

 浏览型号AD809BR-REEL7的Datasheet PDF文件第2页浏览型号AD809BR-REEL7的Datasheet PDF文件第3页浏览型号AD809BR-REEL7的Datasheet PDF文件第4页浏览型号AD809BR-REEL7的Datasheet PDF文件第5页浏览型号AD809BR-REEL7的Datasheet PDF文件第6页浏览型号AD809BR-REEL7的Datasheet PDF文件第7页 
a
155.52 MHz Frequency Synthesizer  
AD809  
FEATURES  
155.52 Mbps ports. The AD809 can be applied to create the trans-  
mit bit clock for one or more ports.  
Frequency Synthesis to 155.52 MHz  
19.44 MHz or 9.72 MHz Input  
Reference Signal Select Mux  
Single Supply Operation: +5 V or –5.2 V  
Output Jitter: 2.0 Degrees RMS  
Low Power: 90 mW  
10 KH ECL/PECL Compatible Output  
10 KH ECL/PECL/TTL/CMOS Compatible Input  
Package: 16-Pin Narrow 150 Mil SOIC  
An input signal multiplexer supports loop-timed applications  
where a 155.52 MHz transmit bit clock is recovered from the  
155.52 Mbps received data.  
The low jitter VCO, low power and wide operating temperature  
range make the device suitable for generating a 155.52 MHz bit  
clock for SONET/SDH/Fiber in the Loop systems.  
The device has a low cost, on-chip VCO that locks to either  
8× or 16× the frequency at the 19.44 MHz or 9.72 MHz input.  
No external components are needed for frequency synthesis; how-  
ever, the user can adjust loop dynamics through selection of a  
damping factor capacitor whose value determines loop damping.  
PRODUCT DESCRIPTION  
The AD809 design guarantees that the clock output frequency  
will drift low (by roughly 20%) in the absence of a signal at the  
input.  
The AD809 provides a 155.52 MHz ECL/PECL output clock from  
either a 19.44 MHz or a 9.72 MHz TTL/CMOS/ECL/PECL refer-  
ence frequency. The AD809 functionality supports a distributed  
timing architecture, allowing a backplane or PCB 19.44 MHz or  
9.72 MHz timing reference signal to be distributed to multiple  
The AD809 consumes 90 mW and operates from a single power  
supply at either +5 V or –5.2 V.  
FUNCTIONAL BLOCK DIAGRAM  
CF1 CF2  
8
7
CLKIN  
13  
12  
(19.44MHz  
OR  
9.72MHz)  
LOOP  
FILTER  
AUTO  
SELECT  
PFD  
VCO  
CLKINN  
BW  
ADJUST  
10  
2
TTL/CMOSIN  
AUTO SELECT  
DIVIDE BY 8/16  
AD809  
5
4
CLKOUT  
PECLIN  
MUX  
(155MHz)  
CLKOUTN  
(155MHz  
PECL  
1
PECLINN  
15  
MUX  
OUTPUT)  
REV. A  
Information furnished by Analog Devices is believed to be accurate and  
reliable. However, no responsibility is assumed by Analog Devices for its  
use, nor for any infringements of patents or other rights of third parties  
which may result from its use. No license is granted by implication or  
otherwise under any patent or patent rights of Analog Devices.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 617/329-4700  
Fax: 617/326-8703  
World Wide Web Site: http://www.analog.com  
© Analog Devices, Inc., 1997  

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