8-Channel, 4.8 kHz, Ultralow Noise,
24-Bit Sigma-Delta ADC with PGA
AD7194
Pressure measurement
Temperature measurement
Flow measurement
Weigh scales
°hromatography
FEATURES
Fast settling filter option
8 differential/16 pseudo differential input channels
RMS noise: 11 nV at 4.7 Hz (gain = 128)
15.5 noise-free bits at 2.4 kHz (gain = 128)
Up to 22 noise-free bits (gain = 1)
Offset drift: 5 nV/ꢀ°
Medical and scientific instrumentation
GENERAL DES°RIPTION
Gain drift: 1 ppm/ꢀ°
The AD7194 is a low noise, complete analog front end for high
precision measurement applications. It contains a low noise,
24-bit sigma-delta (Σ-Δ) analog-to-digital converter (ADC).
The on-chip low noise gain stage means that signals of small
amplitude can interface directly to the ADC.
Programmable gain (1 to 128)
Output data rate: 4.7 Hz to 4.8 kHz
Internal or external clock
Simultaneous 50 Hz/60 Hz rejection
4 general-purpose digital outputs
Power supply
AVDD: 3 V to 5.25 V
DVDD: 2.7 V to 5.25 V
°urrent: 4.65 mA
Temperature range: −40ꢀ° to +105ꢀ°
Package: 32-lead LF°SP
The device can be configured to have eight differential inputs or
sixteen pseudo differential inputs. The on-chip 4.92 MHz clock
can be used as the clock source to the ADC or, alternatively, an
external clock or crystal can be used. The output data rate from
the part can be varied from 4.7 Hz to 4.8 kHz.
The device has a very flexible digital filter, including a fast
settling option. Variables such as output data rate and settling
time are dependent on the option selected. For applications that
require all conversions to be settled, the AD7194 includes zero
latency.
Interface
3-wire serial
SPI, QSPI™, MI°ROWIRE™, and DSP compatible
Schmitt trigger on S°LK
APPLI°ATIONS
The part operates with a power supply from 3 V to 5.25 V. It
consumes a current of 4.65 mA, and it is housed in a 32-lead
LFCSP package.
PL°/D°S analog input modules
Data acquisition
Strain gage transducers
FUN°TIONAL BLO°K DIAGRAM
AV
AGND
DV
DGND
REFIN1(+) REFIN1(–)
DD
DD
REFERENCE
DETECT
AD7194
AIN1/P3
AIN2/P2
AV
DD
AIN3/P1/REFIN2(+)
AIN4/P0/REFIN2(–)
DOUT/RDY
SERIAL
INTERFACE
AND
CONTROL
LOGIC
AIN5
MUX
DIN
Σ-Δ
ADC
PGA
SCLK
CS
AIN16
AINCOM
AGND
TEMP
CLOCK
CIRCUITRY
SENSOR
MCLK1 MCLK2
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2009 Analog Devices, Inc. All rights reserved.
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