AD7190

更新时间： 2024-01-30 14:18:38

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亚德诺 - ADI		/
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21页	177K
描述
4.8 kHz Ultra-Low Noise 24-Bit Sigma-Delta ADC with PGA

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AD7190 技术参数

是否Rohs认证：	符合	生命周期：	Active
包装说明：	TSSOP,	Reach Compliance Code：	compliant
ECCN代码：	EAR99	HTS代码：	8542.39.00.01
风险等级：	5.22	最大模拟输入电压：	5 V
最小模拟输入电压：	-5 V	转换器类型：	ADC, DELTA-SIGMA
JESD-30 代码：	R-PDSO-G24	长度：	7.8 mm
最大线性误差 (EL)：	0.0007%	模拟输入通道数量：	1
位数：	24	功能数量：	1
端子数量：	24	最高工作温度：	105 °C
最低工作温度：	-40 °C	输出位码：	OFFSET BINARY
输出格式：	SERIAL	封装主体材料：	PLASTIC/EPOXY
封装代码：	TSSOP	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	峰值回流温度（摄氏度）：	NOT SPECIFIED
采样速率：	0.0048 MHz	座面最大高度：	1.2 mm
标称供电电压：	5 V	表面贴装：	YES
温度等级：	INDUSTRIAL	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	4.4 mm
Base Number Matches：	1

AD7190 数据手册

4.8 kHz Ultra-Low Noise 24-Bit

Sigma-Delta ADC with PGA

Preliminary Technical Data

AD7190

PLC/DCS Analog Input Modules

Data Acquisition

Medical and Scientific instrumentation

FEATURES

RMS Noise: 7 nV @ 4.7 Hz (gain = 128)

16.5 noise free bits @ 2.4 kHz (gain = 128)

Up to 23 noise free bits (gain = 1)

Offset drift: 5 nV/°C

Gain drift: 2 ppm/°C

Specified drift over time

Programmable gain (1 – 128)

Update rate: 4.7 Hz to 4.8 kHz

Internal or external clock

Simultaneous 50 Hz/60 Hz rejection

Four general purpose digital outputs

Power supply: 3 V to 5.25 V

Current: 6 mA

GENERAL DESCRIPTION

The AD7190 is a low noise, complete analog front end for high

precision measurement applications. It contains a low noise, 24-

bit ∑-∆ ADC. The on-chip low noise gain stage means that

signals of small amplitude can be interfaced directly to the

ADC.

The device can be configured to have two differential inputs or

four pseudo-differential inputs. The device can be operated

with either the internal clock or an external clock. The output

data rate from the part can be varied from 4.7 Hz to 4.8 kHz.

Temperature range: –40°C to +105°C

The device can be operated with a sinc³or a sinc⁴digital filter.

At the lower update rates, the sinc³is useful to optimize the

settling time. The benefit of the sinc⁴at low update rates is the

superior 50 Hz/60 Hz rejection. At the higher update rates, the

sinc⁴filter gives best noise performance. For applications that

require all conversions to be settled, the AD7190 includes a

zero-latency feature.

INTERFACE

3-wire serial

SPI®, QSPI™, MICROWIRE™, and DSP compatible

Schmitt trigger on SCLK

APPLICATIONS

Weigh scales

The part operates with a power supply from 3 V to 5.25 V. It

consumes a current of 6 mA. It is housed in a 24-lead TSSOP

package.

Strain gauge transducers

Pressure measurement

Temperature measurement

Chromatography

FUNCTIONAL BLOCK DIAGRAM

AGND

DGND

REFIN1(+) REFIN1(-)

REFERENCE

DETECT

AD7190

AIN1

AIN2

AIN3

AIN4

DOUT/RDY

DIN

SERIAL

INTERFACE

AND CONTROL

LOGIC

SIGMA DELTA

ADC

PGA

MUX

SCLK

AINCOM

SYNC

BPDSW

AGND

CLOCK

CIRCUITRY

TEMP

SENSOR

AGND

MCLK1

MCLK2

P0/REFIN2(-) P1/REFIN2(+)

Figure 1.

Rev.PrD

7/08

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

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