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AD6620ASZ PDF预览

AD6620ASZ

更新时间: 2024-02-11 22:37:19
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亚德诺 - ADI /
页数 文件大小 规格书
44页 374K
描述
67 MSPS Digital Receive Signal Processor

AD6620ASZ 数据手册

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67 MSPS Digital Receive  
Signal Processor  
a
AD6620  
FUNCTIONAL BLOCK DIAGRAM  
FEATURES  
High Input Sample Rate  
67 MSPS Single Channel Real  
I
I
I
33.5 MSPS Diversity Channel Real  
33.5 MSPS Single Channel Complex  
NCO Frequency Translation  
REAL,  
DUAL REAL,  
OR COMPLEX  
INPUTS  
SERIAL OR  
PARALLEL  
OUTPUTS  
FIR  
FILTER  
CIC  
FILTERS  
OUTPUT  
FORMAT  
Q
Q
Q
Worst Spur Better than –100 dBc  
Tuning Resolution Better than 0.02 Hz  
2nd Order Cascaded Integrator Comb FIR Filter  
Linear Phase, Fixed Coefficients  
Programmable Decimation Rates: 2, 3 . . . 16  
5th Order Cascaded Integrator Comb FIR Filter  
Linear Phase, Fixed Coefficients  
Programmable Decimation Rates: 1, 2, 3 . . . 32  
Programmable Decimating RAM Coefficient FIR Filter  
Up to 134 Million Taps per Second  
256 20-Bit Programmable Coefficients  
Programmable Decimation Rates: 1, 2, 3 . . . 32  
Bidirectional Synchronization Circuitry  
Phase Aligns NCOs  
COS  
–SIN  
P  
OR SERIAL  
CONTROL  
EXTERNAL  
SYNC  
CIRCUITRY  
COMPLEX  
NCO  
JTAG  
PORT  
AD6620  
both narrowband and wideband carriers to be extracted. The  
RAM-based architecture allows easy reconfiguration for multi-  
mode applications.  
Synchronizes Data Output Clocks  
Serial or Parallel Baseband Outputs  
Pin Selectable Serial or Parallel  
The decimating filters remove unwanted signals and noise from  
the channel of interest. When the channel of interest occupies  
less bandwidth than the input signal, this rejection of out-of-  
band noise is called “processing gain.” By using large decimation  
factors, this “processing gain” can improve the SNR of the  
ADC by 36 dB or more. In addition, the programmable RAM  
Coefficient filter allows antialiasing, matched filtering, and  
static equalization functions to be combined in a single, cost-  
effective filter.  
Serial Works with SHARC®, ADSP-21xx, Most Other  
DSPs  
16-Bit Parallel Port, Interleaved I and Q Outputs  
Two Separate Control and Configuration Ports  
Generic P Port, Serial Port  
3.3 V Optimized CMOS Process  
JTAG Boundary Scan  
The input port accepts a 16-bit Mantissa, a 3-bit Exponent,  
and an A/B Select pin. These allow direct interfacing with the  
AD6600, AD6640, AD6644, AD9042 and most other high-  
speed ADCs. Three input modes are provided: Single Channel  
Real, Single Channel Complex, and Diversity Channel Real.  
GENERAL DESCRIPTION  
The AD6620 is a digital receiver with four cascaded signal-  
processing elements: a frequency translator, two fixed-  
coefficient decimating filters, and a programmable coefficient  
decimating filter. All inputs are 3.3 V LVCMOS compatible.  
All outputs are LVCMOS and 5 V TTL compatible.  
When paired with an interleaved sampler such as the AD6600,  
the AD6620 can process two data streams in the Diversity  
Channel Real input mode. Each channel is processed with coher-  
ent frequency translation and output sample clocks. In addition,  
external synchronization pins are provided to facilitate coherent  
frequency translation and output sample clocks among several  
AD6620s. These features can ease the design of systems with  
diversity antennas or antenna arrays.  
As ADCs achieve higher sampling rates and dynamic range, it  
becomes increasingly attractive to accomplish the final IF stage  
of a receiver in the digital domain. Digital IF Processing is less  
expensive, easier to manufacture, more accurate, and more  
flexible than a comparable highly selective analog stage.  
The AD6620 diversity channel decimating receiver is designed  
to bridge the gap between high-speed ADCs and general pur-  
pose DSPs. The high resolution NCO allows a single carrier to  
be selected from a high speed data stream. High dynamic range  
decimation filters with a wide range of decimation rates allow  
Units are packaged in an 80-lead PQFP (plastic quad flatpack)  
and specified to operate over the industrial temperature range  
(–40°C to +85°C).  
SHARC is a registered trademark of Analog Devices, Inc.  
REV. A  
Information furnished by Analog Devices is believed to be accurate and  
reliable. However, no responsibility is assumed by Analog Devices for its  
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat  
may result from its use. No license is granted by implication or otherwise  
under any patent or patent rights of Analog Devices.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781/329-4700  
Fax: 781/326-8703  
www.analog.com  
© Analog Devices, Inc., 2001  

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