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AD645CH PDF预览

AD645CH

更新时间: 2024-01-05 08:07:58
品牌 Logo 应用领域
亚德诺 - ADI 运算放大器放大器电路
页数 文件大小 规格书
8页 441K
描述
Low Noise, Low Drift FET Op Amp

AD645CH 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:TO-99包装说明:HERMETIC SEALED, METAL CAN, HEADER, TO-99, 8 PIN
针数:8Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.31.00.01
风险等级:5.84Is Samacsys:N
放大器类型:OPERATIONAL AMPLIFIER架构:VOLTAGE-FEEDBACK
最大平均偏置电流 (IIB):0.000005 µA25C 时的最大偏置电流 (IIB):0.000005 µA
最小共模抑制比:90 dB标称共模抑制比:110 dB
频率补偿:YES最大输入失调电压:500 µV
JESD-30 代码:O-MBCY-W8JESD-609代码:e0
低-偏置:YES低-失调:NO
负供电电压上限:-18 V标称负供电电压 (Vsup):-15 V
功能数量:1端子数量:8
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:METAL封装代码:TO-99
封装等效代码:CAN8,.2封装形状:ROUND
封装形式:CYLINDRICAL峰值回流温度(摄氏度):NOT SPECIFIED
电源:+-15 V认证状态:Not Qualified
最小摆率:1 V/us标称压摆率:2 V/us
子类别:Operational Amplifier最大压摆率:3.5 mA
供电电压上限:18 V标称供电电压 (Vsup):15 V
表面贴装:NO技术:FET
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:WIRE端子位置:BOTTOM
处于峰值回流温度下的最长时间:NOT SPECIFIED标称均一增益带宽:2000 kHz
最小电压增益:500000Base Number Matches:1

AD645CH 数据手册

 浏览型号AD645CH的Datasheet PDF文件第2页浏览型号AD645CH的Datasheet PDF文件第3页浏览型号AD645CH的Datasheet PDF文件第4页浏览型号AD645CH的Datasheet PDF文件第5页浏览型号AD645CH的Datasheet PDF文件第6页浏览型号AD645CH的Datasheet PDF文件第7页 
Low Noise, Low Drift  
FET Op Amp  
a
AD645  
FEATURES  
CONNECTION DIAGRAMS  
Improved Replacement for Burr-Brown  
OPA-111 and OPA-121 Op Amp  
TO-99 (H) Package  
8-Pin Plastic Mini-DIP  
(N) Package  
CASE  
LOW NOISE  
2 V p-p max, 0.1 Hz to 10 Hz  
10 nV/Hz max at 10 kHz  
11 fA p-p Current Noise 0.1 Hz to 10 Hz  
OFFSET  
NULL  
OFFSET  
NULL  
8
1
2
3
4
8
7
6
5
NC  
+V  
+V  
1
3
7
5
AD645  
–IN  
S
2
– IN  
6
OUTPUT  
HIGH DC ACCURACY  
250 V max Offset Voltage  
1 V/؇C max Drift  
1.5 pA max Input Bias Current  
114 dB Open-Loop Gain  
Available in Plastic Mini-DIP, 8-Pin Header Packages, or  
Chip Form  
+IN  
OUTPUT  
AD645  
4
OFFSET  
NULL  
OFFSET  
NULL  
+IN  
TOP VIEW  
–V  
S
V
NC = NO CONNECT  
NOTE: CASE IS CONNECTED  
TO PIN 8  
The AD645 is available in six performance grades. The AD645J  
and AD645K are rated over the commercial temperature range  
of 0°C to +70°C. The AD645A, AD645B, and the ultra-  
precision AD645C are rated over the industrial temperature  
range of –40°C to +85°C. The AD645S is rated over the military  
temperature range of –55°C to +125°C and is available  
processed to MIL-STD-883B.  
APPLICATIONS  
Low Noise Photodiode Preamps  
CT Scanners  
Precision I-V Converters  
PRODUCT DESCRIPTION  
The AD645 is available in an 8-pin plastic mini-DIP, 8-pin  
header, or in die form.  
The AD645 is a low noise, precision FET input op amp. It of-  
fers the pico amp level input currents of a FET input device  
coupled with offset drift and input voltage noise comparable to a  
high performance bipolar input amplifier.  
PRODUCT HIGHLIGHTS  
1. Guaranteed and tested low frequency noise of 2 µV p-p max  
and 20 nV/Hz at 100 Hz makes the AD645C ideal for low  
noise applications where a FET input op amp is needed.  
The AD645 has been improved to offer the lowest offset drift in  
a FET op amp, 1 µV/°C. Offset voltage drift is measured and  
trimmed at wafer level for the lowest cost possible. An inher-  
ently low noise architecture and advanced manufacturing tech-  
niques result in a device with a guaranteed low input voltage  
noise of 2 µV p-p, 0.1 Hz to 10 Hz. This level of dc performance  
along with low input currents make the AD645 an excellent  
choice for high impedance applications where stability is of  
prime concern.  
2. Low VOS drift of 1 µV/°C max makes the AD645C an excel-  
lent choice for applications requiring ultimate stability.  
3. Low input bias current and current noise (11 fA p-p 0.1 Hz to  
10 Hz) allow the AD645 to be used as a high precision  
preamp for current output sensors such as photodiodes, or as  
a buffer for high source impedance voltage output sensors.  
30  
25  
20  
1k  
100  
15  
10  
10  
5
0
1.0  
–2.5 –2.0 –1.5 –1.0 –0.5  
0.0  
0.5  
1.0  
1.5  
2.0  
2.5  
1
10  
100  
1k  
10k  
FREQUENCY – Hz  
INPUT OFFSET VOLTAGE DRIFT– µV/  
°C  
Figure 1. AD645 Voltage Noise Spectral Density vs.  
Frequency  
Figure 2. Typical Distribution of Average Input Offset  
Voltage Drift (196 Units)  
REV. B  
Information furnished by Analog Devices is believed to be accurate and  
reliable. However, no responsibility is assumed by Analog Devices for its  
use, nor for any infringements of patents or other rights of third parties  
which may result from its use. No license is granted by implication or  
otherwise under any patent or patent rights of Analog Devices.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 617/329-4700  
Fax: 617/326-8703  

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