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AD642S

更新时间: 2024-02-23 14:12:11
品牌 Logo 应用领域
亚德诺 - ADI 运算放大器
页数 文件大小 规格书
6页 398K
描述
Precision, Low Cost Dual BiFET Op Amp

AD642S 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:TO-99包装说明:TO-99, CAN8,.2
针数:8Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.33.00.01
风险等级:5.73放大器类型:OPERATIONAL AMPLIFIER
架构:VOLTAGE-FEEDBACK最大平均偏置电流 (IIB):0.000035 µA
最小共模抑制比:80 dB标称共模抑制比:80 dB
频率补偿:YES最大输入失调电压:3500 µV
JESD-30 代码:O-MBCY-W8JESD-609代码:e0
低-偏置:YES低-失调:NO
微功率:YES负供电电压上限:-15 V
标称负供电电压 (Vsup):-15 V功能数量:2
端子数量:8最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:METAL
封装代码:TO-99封装等效代码:CAN8,.2
封装形状:ROUND封装形式:CYLINDRICAL
电源:+-15 V认证状态:Not Qualified
最小摆率:2 V/us标称压摆率:3 V/us
子类别:Operational Amplifier最大压摆率:2.8 mA
供电电压上限:15 V标称供电电压 (Vsup):15 V
表面贴装:NO技术:BIPOLAR
温度等级:MILITARY端子面层:Tin/Lead (Sn63Pb37)
端子形式:WIRE端子位置:BOTTOM
标称均一增益带宽:1000 kHz最小电压增益:100000
Base Number Matches:1

AD642S 数据手册

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Precision, Low Cost  
Dual BiFET Op Amp  
a
AD642  
PIN CONFIGURATION  
FEATURES  
Matched Offset Voltage  
Matched Offset Voltage Over Temperature  
Matched Bias Current  
Crosstalk: –124 dB @ 1 kHz  
Low Bias Current: 35 pA max Warmed Up  
Low Offset Voltage: 500 V max  
Low Input Voltage Noise: 2 V p-p  
High Open Loop Gain  
Low Quiescent Current: 2.8 mA max  
Low Total Harmonic Distortion  
Standard Dual Amplifier Pin Out  
Available in Hermetic Metal Can Package and Chip Form  
MIL-STD-883B Processing Available  
Single Version Available: AD542  
PRODUCT DESCRIPTION  
The AD642 is available in four versions: the ‘‘J’’, ‘‘K’’ and ‘‘L,’’  
all specified over the 0°C to +70°C temperature range and one  
version, ‘‘S,’’ over the –55°C to +125°C extended operating  
temperature range. All devices are packaged in the hermetically-  
sealed, TO-99 metal can or available in chip form.  
The AD642 is a pair of matched high speed monolithic BiFET  
operational amplifier fabricated with the most advanced bipolar,  
JFET and laser trimming technologies. The AD642 offers  
matched bias currents that are significantly lower than currently  
available monolithic dual FET input operational amplifiers:  
35 pA max matched to 25 pA for the AD642K and L; 75 pA  
max, matched to 35 pA for the AD642J and S. In addition, the  
offset voltage is laser trimmed to less than 0.5 mV and matched  
to 0.25 mV for the AD642L, 1.0 mV and matched to 0.5 mV for  
the AD642K, utilizing Analog’s laser-wafer trimming (LWT)  
process.  
PRODUCT HIGHLIGHTS  
1. The AD642 has tight matching specifications to ensure high  
performance, eliminating the need to match individual  
devices.  
2. Analog Devices, unlike some manufacturers, specifies each  
device for the maximum bias current at either input in the  
warmed-up condition, thus assuring the user that the AD642  
will meet its published specifications in actual use.  
The tight matching and temperature tracking between the  
operational amplifiers is achieved by ion-implanted JFETs and  
laser-wafer trimming. Ion-implantation permits the fabrication of  
precision, matched JFETs on a monolithic bipolar chip. The  
optimizes the process to product matched bias currents which  
have lower initial bias currents than other popular BiFET op  
amps. Laser-wafer trimming each amplifier’s input offset voltage  
assures tight initial match and combined with superior IC  
processing guarantees offset voltage tracking over the tempera-  
ture range.  
3. Laser-wafer-trimming reduces offset voltage to as low as  
0.5 mV max and matched side to side to 0.25 mV  
(AD642L), thus eliminating the need for external nulling.  
4. Low voltage noise (2 µV, p-p), and high open loop gain  
enhance the AD642’s performance as a precision op amp.  
5. The standard dual amplifier pin out allows the AD642 to  
replace lower performance duals without redesign.  
The AD642 is recommended for applications in which excellent  
ac and dc performance is required. The matched amplifiers  
provide a low-cost solution for true instrumentation amplifiers,  
log ratio amplifiers, and output amplifiers for four quadrant  
multiplying D/A converters such as the AD7541.  
6. The AD642 is available in chip form.  
REV. 0  
Information furnished by Analog Devices is believed to be accurate and  
reliable. However, no responsibility is assumed by Analog Devices for its  
use, nor for any infringements of patents or other rights of third parties  
which may result from its use. No license is granted by implication or  
otherwise under any patent or patent rights of Analog Devices.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 617/329-4700  
Fax: 617/326-8703  

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