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AD6121ACP

更新时间： 2024-01-08 19:40:03
品牌 Logo 应用领域
亚德诺 - ADI 稳压器电信集成电路电信电路信息通信管理接收机PC
页数 文件大小 规格书
16页 259K
描述
CDMA 3 V Receiver IF Subsystem with Integrated Voltage Regulator

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AD6121ACP 技术参数

是否无铅：含铅是否Rohs认证：不符合
生命周期：Obsolete零件包装代码：SSOP
包装说明：SSOP-28针数：28
Reach Compliance Code：not_compliantECCN代码：5A991.G
HTS代码：8542.39.00.01风险等级：5.88
Is Samacsys：NJESD-30 代码：R-XDSO-G28
JESD-609代码：e0长度：10.2 mm
功能数量：1端子数量：28
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：UNSPECIFIED封装代码：SSOP
封装等效代码：SSOP28,.3封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, SHRINK PITCH峰值回流温度（摄氏度）：NOT SPECIFIED
电源：3 V认证状态：Not Qualified
座面最大高度：1.98 mm子类别：Other Telecom ICs
标称供电电压：3 V表面贴装：YES
技术：BICMOS电信集成电路类型：TELECOM CIRCUIT
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：5.3 mmBase Number Matches：1

AD6121ACP 数据手册

 浏览型号AD6121ACP的Datasheet PDF文件第2页浏览型号AD6121ACP的Datasheet PDF文件第3页浏览型号AD6121ACP的Datasheet PDF文件第4页浏览型号AD6121ACP的Datasheet PDF文件第5页浏览型号AD6121ACP的Datasheet PDF文件第6页浏览型号AD6121ACP的Datasheet PDF文件第7页 
CDMA 3 V Receiver IF Subsystem  
with Integrated Voltage Regulator  
a
AD6121  
FEATURES  
GENERAL DESCRIPTION  
Fully Compliant with IS98A and PCS Specifications  
CDMA, W-CDMA, AMPS, and TACS Operation  
Linear IF Amplifier  
5.9 dB Noise Figure  
–47.5 dB to +47 dB Linear-in-dB Gain Control  
Quadrature Demodulator  
The AD6121 is a low power receiver IF subsystem specifically  
designed for CDMA applications. It consists of high dynamic  
range IF amplifiers with voltage controlled gain, a divide-by-two  
quadrature generator, an I and Q demodulator, and a power-  
down control input. An integral low dropout regulator allows  
operation from battery voltages from 2.9 V to 4.2 V.  
Demodulates IFs from 50 MHz to 350 MHz  
Integral Low Dropout Regulator  
200 mV Voltage Drop  
Accepts 2.9 V to 4.2 V Input from Battery  
Low Power  
The gain control input accepts an external gain control voltage  
input from a DAC. It provides 94.5 dB of gain control with a  
nominal 52.5 dB/V scale factor when using an internal voltage  
reference. The gain control interface reference input can be  
connected to either the internal reference or an external reference.  
10 mA at Midgain  
The I and Q demodulator provides differential quadrature base-  
band outputs to interface with CDMA baseband converters. A  
divide-by-two quadrature generator followed by dual polyphase  
filters ensures maximum 2.5° quadrature accuracy.  
<1 ␮A Sleep Mode Operation  
Companion Transmitter IF Chip Available (AD6122)  
APPLICATIONS  
CDMA, W-CDMA, AMPS, and TACS Operation  
QPSK Receivers  
The AD6121 IF Subsystem is fabricated using a 25 GHz ft  
BiCMOS silicon process and is packaged in a 28-lead SSOP  
and a 32-leadless LPCC chip scale package (5 mm × 5 mm).  
FUNCTIONAL BLOCK DIAGRAM  
ROOFING  
FILTER  
IF  
DEMODULATOR  
INPUT  
OUTPUT  
IOUT  
CDMA  
INPUT  
IOUT  
IF AMPLIFIERS  
I
LOCAL  
OSCILLATOR  
INPUT  
2
Q
QOUT  
AD6121  
FM  
INPUT  
QOUT  
QUADRATURE DEMODULATOR  
INPUT STAGE  
VPOS  
LOW  
DROPOUT  
REGULATOR  
VREG  
PTAT  
TEMPERATURE  
COMPENSATION  
GAIN CONTROL  
SCALE FACTOR  
POWER- POWER-  
DOWN 2 DOWN 1  
CONTROL REFERENCE  
CDMA/FM  
SELECT  
GAIN  
CONTROL  
VOLTAGE  
INPUT  
GAIN  
1.23V  
VOLTAGE  
REFERENCE  
INPUT  
OUTPUT  
REV. B  
Information furnished by Analog Devices is believed to be accurate and  
reliable. However, no responsibility is assumed by Analog Devices for its  
use, nor for any infringements of patents or other rights of third parties  
which may result from its use. No license is granted by implication or  
otherwise under any patent or patent rights of Analog Devices.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781/329-4700  
Fax: 781/326-8703  
World Wide Web Site: http://www.analog.com  
© Analog Devices, Inc., 2000  
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