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AD608ARZ-RL

更新时间: 2024-01-31 06:19:39
品牌 Logo 应用领域
亚德诺 - ADI 电信集成电路光电二极管限制器
页数 文件大小 规格书
16页 326K
描述
Low Power Mixer/Limiter/RSSI 3 V Receiver IF Subsystem

AD608ARZ-RL 技术参数

是否无铅: 含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:SOIC
包装说明:SOP,针数:16
Reach Compliance Code:compliantECCN代码:5A991.B
HTS代码:8542.39.00.01风险等级:0.63
JESD-30 代码:R-PDSO-G16JESD-609代码:e3
长度:9.9 mm湿度敏感等级:1
功能数量:1端子数量:16
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260认证状态:Not Qualified
座面最大高度:1.75 mm标称供电电压:3 V
表面贴装:YES电信集成电路类型:TELECOM CIRCUIT
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:3.9 mmBase Number Matches:1

AD608ARZ-RL 数据手册

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Low Power Mixer/Limiter/RSSI  
3 V Receiver IF Subsystem  
AD608  
The RF and local oscillator (LO) bandwidths both exceed  
500 MHz. In a typical IF application, the AD608 can accept the  
output of a 240 MHz surface acoustic wave (SAW) filter and down-  
convert it to a nominal 10.7 MHz IF with a conversion gain of  
24 dB (ZIF = 165 Ω). The AD608 logarithmic/limiting amplifier  
section handles any IF from low frequency (LF) up to 30 MHz.  
FEATURES  
Mixer  
−15 dBm, 1 dB compression point  
−5 dBm IP3  
24 dB conversion gain  
>500 MHz input bandwidth  
Logarithmic/limiting amplifier  
80 dB RSSI range  
3ꢀ phase stability over 80 dB range  
Low power  
The mixer is a doubly balanced gilbert-cell mixer and operates  
linearly for RF inputs spanning −95 dBm to −15 dBm. It has a  
nominal −5 dBm third-order intercept. An on-board LO pre-  
amplifier requires only −16 dBm of LO drive. The current output  
of the mixer drives a reverse-terminated, industry-standard  
10.7 MHz, 330 Ω filter.  
21 mW at 3 V power consumption  
CMOS-compatible power-down to 300 μW typical  
200 ns enable/disable time  
The nominal logarithmic scaling is such that the output is +0.2 V  
for a sinusoidal input to the IF amplifier of −75 dBm and +1.8 V  
at an input of +5 dBm; over this range, the logarithmic confor-  
mance is typically 1 dB. The logarithmic slope is proportional  
to the supply voltage. A feedback loop automatically nulls the  
input offset of the first stage down to the submicrovolt level.  
APPLICATIONS  
PHS, GSM, TDMA, FM, or PM receivers  
Battery-powered instrumentation  
Base station RSSI measurements  
The AD608 limiter output provides a hard-limited signal output  
at 400 mV p-p. The voltage gain of the limiting amplifier to this  
output is more than 100 dB. Transition times are 11 ns and the  
phase is stable to within 3ꢀ at 10.7 MHz for signals from −75 dBm  
to +5 dBm.  
GENERAL DESCRIPTION  
The AD608 provides a low power, low distortion, low noise mixer  
as well as a complete, monolithic logarithmic/limiting amplifier  
that uses a successive-detection technique. In addition, the AD608  
provides both a high speed received signal strength indicator  
(RSSI) output with 80 dB dynamic range and a hard-limited  
output. The RSSI output is from a two-pole postdemodulation  
low-pass filter and provides a loadable output voltage of 0.2 V to  
1.8 V. The AD608 operates from a single 2.7 V to 5.5 V supply  
at a typical power level of 21 mW at 3 V.  
The AD608 is enabled by a CMOS logic-level voltage input,  
with a response time of 200 ns. When disabled, the standby  
power is reduced to 300 μW within 400 ns.  
The AD608 is specified for the industrial temperature range of  
−25ꢀC to +85ꢀC for 2.7 V to 5.5 V supplies and −40ꢀC to +85ꢀC for  
3.0 V to 5.5 V supplies. This device comes in a 16-lead plastic SOIC.  
FUNCTIONAL BLOCK DIAGRAM  
3dB NOMINAL  
INSERTION LOSS  
110dB LIMITER GAIN  
90dB RSSI  
24dB MIXER GAIN  
RSSI OUTPUT  
20mV/dB  
RSSI  
7 FULL-WAVE  
IF INPUT  
11  
12  
±6mA MAX OUTPUT  
(±890mV INTO 165)  
RECTIFIER CELLS  
–75dBm TO  
0.2V TO 1.8V  
2
+15dBm  
2MHz  
LPF  
5
6
RFHI  
COM3  
VPS2  
MIXER  
10.7MHz  
BAND-PASS  
FILTER  
IFHI  
RF INPUT  
MXOP  
–95dBm TO  
7
8
9
14 +2.7V TO 5.5V  
1
–15dBm  
BPF  
DRIVER  
LMOP  
5-STAGE IF AMPLIFIER  
(16dB PER STAGE)  
330Ω  
15 LIMITER  
OUTPUT  
400mV p-p  
330Ω  
RFLO  
10nF  
LO  
PREAMP  
VMID  
FINAL  
LIMITER  
10  
13  
+
IFLO  
100nF  
100Ω  
MIDSUPPLY  
IF BIAS  
FDBK  
18nF  
±50µA  
BIAS  
AD608  
VPS1 COM1  
LOHI COM2  
4
PRUP  
1
2
3
16  
2.7V TO  
5.5V  
LO INPUT  
–16dBm  
CMOS LOGIC  
INPUT  
1
–15dBm = ±56mV MAXIMUM FOR LINEAR OPERATION.  
39.76µV RMS TO 397.6mV RMS FOR ±1dB RSSI ACCURACY.  
2
Figure 1.  
Rev. C  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rights of third parties that may result from its use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks and registeredtrademarks arethe property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700 www.analog.com  
Fax: 781.461.3113 ©1996–2009 Analog Devices, Inc. All rights reserved.  
 

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