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AD5382BSTZ-5

更新时间: 2024-02-05 09:07:50
品牌 Logo 应用领域
亚德诺 - ADI 转换器数模转换器
页数 文件大小 规格书
40页 1170K
描述
40-Channel, 3 V/5 V, Single-Supply 12-Bit, denseDAC

AD5382BSTZ-5 技术参数

是否无铅: 含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:QFP
包装说明:LFQFP, QFP100,.63SQ,20针数:100
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:2.15
最大模拟输出电压:5.5 V最小模拟输出电压:
转换器类型:D/A CONVERTER输入位码:BINARY
输入格式:PARALLEL, WORDJESD-30 代码:S-PQFP-G100
JESD-609代码:e3长度:14 mm
最大线性误差 (EL):0.0244%湿度敏感等级:3
位数:14功能数量:1
端子数量:100最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:LFQFP封装等效代码:QFP100,.63SQ,20
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE, FINE PITCH
峰值回流温度(摄氏度):260电源:3/5,5 V
认证状态:Not Qualified座面最大高度:1.6 mm
最大稳定时间:10 µs标称安定时间 (tstl):8 µs
子类别:Other Converters最大压摆率:0.475 mA
标称供电电压:5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:40宽度:14 mm
Base Number Matches:1

AD5382BSTZ-5 数据手册

 浏览型号AD5382BSTZ-5的Datasheet PDF文件第2页浏览型号AD5382BSTZ-5的Datasheet PDF文件第3页浏览型号AD5382BSTZ-5的Datasheet PDF文件第4页浏览型号AD5382BSTZ-5的Datasheet PDF文件第5页浏览型号AD5382BSTZ-5的Datasheet PDF文件第6页浏览型号AD5382BSTZ-5的Datasheet PDF文件第7页 
40-Channel, 3 V/5 V, Single-Supply,  
12-Bit, denseDAC®  
Data Sheet  
AD5381  
FEATURES  
Guaranteed monotonic  
INTEGRATED FUNCTIONS  
Channel monitor  
Simultaneous output update via  
LDAC  
INL error: 1 LSB max  
On-chip 1.25 V/2.5 V, 10 ppm/°C reference  
Temperature range: –40°C to +85°C  
Rail-to-rail output amplifier  
Power-down  
Clear function to user-programmable code  
Amplifier boost mode to optimize slew rate  
User-programmable offset and gain adjust  
Toggle mode enables square wave generation  
Thermal monitors  
Package type: 100-lead LQFP (14 mm × 14 mm)  
User interfaces:  
APPLICATIONS  
Variable optical attenuators (VOAs)  
Parallel  
Serial (SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible,  
featuring data readback)  
I2C®-compatible  
Level setting (ATE)  
Optical micro-electro-mechanical systems (MEMs)  
Control systems  
Robust 6.5 kV HBM and 2 kV FICDM ESD rating  
Instrumentation  
FUNCTIONAL BLOCK DIAGRAM  
DVDD (×3)  
DGND (×3)  
AVDD (×5)  
AGND (×5)  
DAC_GND (×5)  
REFGND  
REFOUT/REFIN SIGNAL_GND (×5)  
PD  
SER/PAR  
AD5381  
1.25V/2.5V  
REFERENCE  
FIFO EN  
CS/(SYNC/AD0)  
WR/(DCEN/AD1)  
SDO  
12  
12  
12  
12  
12  
12  
12  
12  
12  
12  
12  
12  
12  
INPUT  
REG0  
DAC  
REG0  
DAC 0  
VOUT0  
DB11/(DIN/SDA)  
12  
12  
m REG0  
c REG0  
DB10/(SCLK/SCL)  
FIFO  
+
STATE  
MACHINE  
+
2
DB9/(SPI/I C)  
R
R
R
R
R
R
R
R
DB8  
INTERFACE  
CONTROL  
LOGIC  
12  
INPUT  
REG1  
DAC  
REG1  
DAC 1  
DB0  
CONTROL  
LOGIC  
VOUT1  
VOUT2  
VOUT3  
VOUT4  
VOUT5  
VOUT6  
12  
12  
A5  
A0  
m REG1  
c REG1  
REG0  
REG1  
RESET  
BUSY  
CLR  
12  
INPUT  
REG6  
DAC  
REG6  
DAC 6  
POWER-ON  
RESET  
12  
12  
m REG6  
c REG6  
12  
INPUT  
REG7  
DAC  
REG7  
VOUT0………VOUT38  
DAC 7  
VOUT7  
VOUT8  
12  
12  
m REG7  
c REG7  
39-TO-1  
MUX  
VOUT38  
×5  
VOUT39/MON_OUT  
LDAC  
Figure 1.  
Rev. D  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rights of third parties that may result from its use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks and registered trademarks are the property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700 www.analog.com  
Fax: 781.461.3113 ©2004–2012 Analog Devices, Inc. All rights reserved.  

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