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AD5379

更新时间: 2024-01-17 21:34:14
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
28页 393K
描述
40-Channel, 14-Bit, Parallel and Serial Input, Bipolar Voltage-Output DAC

AD5379 技术参数

是否无铅: 含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:BGA
包装说明:BGA, BGA108,12X12,40针数:108
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.64
最大模拟输出电压:14.5 V最小模拟输出电压:-1 V
转换器类型:D/A CONVERTER输入位码:BINARY
输入格式:SERIAL, PARALLEL, WORDJESD-30 代码:S-PBGA-B108
JESD-609代码:e1长度:13 mm
最大线性误差 (EL):0.0183%湿度敏感等级:3
标称负供电电压:-12 V位数:14
功能数量:1端子数量:108
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:BGA
封装等效代码:BGA108,12X12,40封装形状:SQUARE
封装形式:GRID ARRAY峰值回流温度(摄氏度):260
电源:3/5,+-12/+-15 V认证状态:Not Qualified
座面最大高度:1.85 mm最大稳定时间:30 µs
标称安定时间 (tstl):20 µs子类别:Other Converters
标称供电电压:12 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Silver/Copper (Sn96.5Ag3.0Cu0.5)端子形式:BALL
端子节距:1 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:40宽度:13 mm
Base Number Matches:1

AD5379 数据手册

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40-Channel, 14-Bit, Parallel and  
Serial Input, Bipolar Voltage-Output DAC  
AD5379  
Interface options:  
FEATURES  
Parallel interface  
40-channel DAC in 13 mm × 13 mm 108-lead CSPBGA  
Guaranteed monotonic to 14 bits  
Buffered voltage outputs  
Output voltage span of 3.5 V × VREF(+)  
Maximum output voltage span of 17.5 V  
DSP/microcontroller-compatible 3-wire serial interface  
2.5 V to 5.5 V JEDEC-compliant digital levels  
SDO daisy-chaining option  
Power-on reset  
Digital reset (RESET pin and soft reset function)  
System calibration function allowing user-programmable  
offset and gain  
Pseudo differential outputs relative to REFGND  
Clear function to user-defined REFGND (CLR pin)  
Simultaneous update of DAC outputs (LDAC pin)  
DAC increment/decrement mode  
APPLICATIONS  
Level setting in automatic test equipment (ATE)  
Variable optical attenuators (VOA)  
Optical switches  
Channel grouping and addressing features  
Industrial control systems  
FUNCTIONAL BLOCK DIAGRAM  
V
V
V
AGND  
DGND  
LDAC  
V
V
1(+)  
V
1(–) REFGND A1  
CC  
DD  
SS  
BIAS  
REF  
REF  
VBIAS  
AD5379  
POWER-ON  
RESET  
CLR  
RESET  
FIFOEN  
DCEN/WR  
VOUT 0  
VOUT 1  
INPUT  
REG  
0–1  
DAC  
REG  
0–1  
14  
14  
14  
14  
14  
14  
DAC 0–1  
SYNC/CS  
REG0  
/
/
/
/
/
/
m REG0–1  
c REG0–1  
REG1  
14  
/
DB13  
SCLK/DB12  
DIN/DB11  
INPUT  
REG  
2
DAC  
REG  
2
14  
/
14  
/
DAC 2  
VOUT 2  
DB0  
m REG2  
c REG2  
VOUT 3  
VOUT 4  
14  
A7  
/
14  
/
VOUT 5  
VOUT 6  
VOUT 7  
A0  
INPUT  
REG  
7
DAC  
REG  
7
14  
14  
14  
14  
SER/PAR  
DIN  
DAC 7  
/
/
/
/
/
/
SCLK  
SDO  
m REG7  
c REG7  
14  
/
REFGND B1  
REFGND B2  
REFGND C1  
REFGND C2  
REFGND D1  
REFGND D2  
VOUT 8  
INPUT  
REG  
8–9  
DAC  
REG  
8–9  
14  
/
14  
/
14  
14  
DAC 8–9  
VOUT 9  
VOUT 10  
m REG8–9  
c REG8–9  
14  
/
×4  
VOUT 39  
BUSY  
V
2(+)  
V
2(–) REFGND A2  
REF  
REF  
Figure 1.  
AD5379—Protected by U.S. Patent No. 5,969,657; other patents pending.  
Rev. 0  
Information furnished by Analog Devices is believed to be accurate and reliable.  
However, no responsibility is assumed by Analog Devices for its use, nor for any  
infringements of patents or other rights of third parties that may result from its use.  
Specifications subject to change without notice. No license is granted by implication  
or otherwise under any patent or patent rights of Analog Devices. Trademarks and  
registered trademarks are the property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Fax: 781.326.8703  
www.analog.com  
© 2004 Analog Devices, Inc. All rights reserved.  

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