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AD5341BRU-REEL

更新时间： 2024-01-01 06:07:38
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
28页 542K
描述
2.5 V to 5.5 V, 115 μA, Parallel Interface Single Voltage-Output 8-/10-/12-Bit DACs

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AD5341BRU-REEL 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：TSSOP
包装说明：TSSOP,针数：20
Reach Compliance Code：unknown风险等级：5.46
转换器类型：D/A CONVERTER输入位码：BINARY
输入格式：PARALLEL, WORDJESD-30 代码：R-PDSO-G20
JESD-609代码：e3长度：6.5 mm
湿度敏感等级：1位数：12
功能数量：1端子数量：20
最高工作温度：105 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：260认证状态：COMMERCIAL
座面最大高度：1.2 mm标称安定时间 (tstl)：8 µs
标称供电电压：3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：MATTE TIN端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：40宽度：4.4 mm

AD5341BRU-REEL 数据手册

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2.5 V to 5.5 V, 115 μA, Parallel Interface  
Single Voltage-Output 8-/10-/12-Bit DACs  
AD5330/AD5331/AD5340/AD5341  
FEATURES  
GENERAL DESCRIPTION  
AD5330: single 8-bit DAC in 20-lead TSSOP  
AD5331: single 10-bit DAC in 20-lead TSSOP  
AD5340: single 12-bit DAC in 24-lead TSSOP  
AD5341: single 12-bit DAC in 20-lead TSSOP  
Low power operation: 115 μA @ 3 V, 140 μA @ 5 V  
The AD5330/AD5331/AD5340/AD53411 are single 8-/10-/12-  
bit DACs. They operate from a 2.5 V to 5.5 V supply consuming  
just 115 μA at 3 V and feature a power-down mode that further  
reduces the current to 80 nA. The devices incorporate an on-chip  
output buffer that can drive the output to both supply rails, but  
PD  
Power-down to 80 nA @ 3 V, 200 nA @ 5 V via  
2.5 V to 5.5 V power supply  
Pin  
the AD5330, AD5340, and AD5341 allow a choice of buffered  
or unbuffered reference input.  
Double-buffered input logic  
The AD5330/AD5331/AD5340/AD5341 have a parallel  
Guaranteed monotonic by design over all codes  
Buffered/unbuffered reference input options  
Output range: 0 V to VREF or 0 V to 2 × VREF  
Power-on reset to 0 V  
CS  
interface.  
input registers on the rising edge of  
The GAIN pin allows the output range to be set at 0 V to VREF or  
0 V to 2 × VREF  
Input data to the DACs is double-buffered, allowing simultane-  
LDAC  
selects the device and data is loaded into the  
WR  
.
LDAC  
.
Simultaneous update of DAC outputs via  
CLR  
pin  
Asynchronous  
facility  
Low power parallel data interface  
On-chip rail-to-rail output buffer amplifiers  
Temperature range: −40°C to +105°C  
ous update of multiple DACs in a system using the  
pin.  
input is also provided, which resets the  
CLR  
An asynchronous  
contents of the input register and the DAC register to all zeros.  
These devices also incorporate a power-on reset circuit that  
ensures that the DAC output powers on to 0 V and remains  
there until valid data is written to the device.  
APPLICATIONS  
Portable battery-powered instruments  
Digital gain and offset adjustment  
Programmable voltage and current sources  
Programmable attenuators  
The AD5330/AD5331/AD5340/AD5341 are available in thin  
shrink small outline packages (TSSOP).  
Industrial process control  
1 Protected by U.S. Patent Number 5,969,657.  
FUNCTIONAL BLOCK DIAGRAM  
V
V
DD  
REF  
3
12  
POWER-ON  
RESET  
AD5330  
BUF  
GAIN  
DB  
1
8
DAC  
REGISTER  
INPUT  
REGISTER  
8-BIT  
DAC  
20  
13  
4
BUFFER  
7
0
V
OUT  
.
.
DB  
6
7
CS  
WR  
CLR  
RESET  
POWER-DOWN  
LOGIC  
9
10  
LDAC  
11  
5
PD GND  
Figure 1. AD5330  
Rev. A  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rights of third parties that may result from its use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks and registeredtrademarks arethe property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700 www.analog.com  
Fax: 781.461.3113 ©2000–2008 Analog Devices, Inc. All rights reserved.  
 
 
 
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