AD5302

更新时间： 2024-02-01 12:56:18

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
16页	211K
描述
+2.5 V to +5.5 V, 230 uA Dual Rail-to-Rail, Voltage Output 8-/10-/12-Bit DACs

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AD5302 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	TSSOP
包装说明：	TSSOP,	针数：	10
Reach Compliance Code：	unknown	风险等级：	5.7
Is Samacsys：	N	最大模拟输出电压：	5.499 V
最小模拟输出电压：	0.001 V	转换器类型：	D/A CONVERTER
输入位码：	BINARY	输入格式：	SERIAL
JESD-30 代码：	S-PDSO-G10	JESD-609代码：	e3
长度：	3 mm	最大线性误差 (EL)：	0.1953%
湿度敏感等级：	1	位数：	8
功能数量：	1	端子数量：	10
最高工作温度：	105 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	TSSOP
封装形状：	SQUARE	封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：	260	认证状态：	COMMERCIAL
座面最大高度：	1.1 mm	标称安定时间 (tstl)：	6 µs
标称供电电压：	3 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	MATTE TIN	端子形式：	GULL WING
端子节距：	0.5 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	40	宽度：	3 mm
Base Number Matches：	1

AD5302 数据手册

+2.5 V to +5.5 V, 230 ␮A Dual Rail-to-Rail,

Voltage Output 8-/10-/12-Bit DACs

AD5302/AD5312/AD5322*

FEATURES

GENERAL DESCRIPTION

AD5302: Two 8-Bit Buffered DACs in One Package

AD5312: Two 10-Bit Buffered DACs in One Package

AD5322: Two 12-Bit Buffered DACs in One Package

10-Lead ␮SOIC Package

Micropower Operation: 300 ␮A @ 5 V (Including

Reference Current)

Power-Down to 200 nA @ 5 V, 50 nA @ 3 V

+2.5 V to +5.5 V Power Supply

Double-Buffered Input Logic

The AD5302/AD5312/AD5322 are dual 8-, 10- and 12-bit buff-

ered voltage output DACs in a 10-lead µSOIC package that

operate from a single +2.5 V to +5.5 V supply consuming

230 µA at 3 V. Their on-chip output amplifiers allow the outputs

to swing rail-to-rail with a slew rate of 0.7 V/µs. The AD5302/

AD5312/AD5322 utilize a versatile 3-wire serial interface which

operates at clock rates up to 30 MHz and is compatible with

standard SPI™, QSPI™, MICROWIRE™ and DSP interface

standards.

Guaranteed Monotonic By Design Over All Codes

Buffered/Unbuffered Reference Input Options

0–V_REFOutput Voltage

The references for the two DACs are derived from two reference

pins (one per DAC). The reference inputs may be configured as

buffered or unbuffered inputs. The outputs of both DACs may

be updated simultaneously using the asynchronous LDAC in-

put. The parts incorporate a power-on-reset circuit that ensures

that the DAC outputs power-up to 0 V and remain there until a

valid write takes place to the device. The parts contain a power-

down feature that reduces the current consumption of the

devices to 200 nA at 5 V (50 nA at 3 V) and provides software-

selectable output loads while in power-down mode.

Power-On-Reset to Zero Volts

Simultaneous Update of DAC Outputs via LDAC

Low Power Serial Interface with Schmitt-Triggered

Inputs

On-Chip Rail-to-Rail Output Buffer Amplifiers

APPLICATIONS

Portable Battery-Powered Instruments

Digital Gain and Offset Adjustment

Programmable Voltage and Current Sources

Programmable Attenuators

The low power consumption of these parts in normal operation

make them ideally suited to portable battery operated equip-

ment. The power consumption is 1.5 mW at 5 V, 0.7 mW at

3 V, reducing to 1 µW in power-down mode.

FUNCTIONAL BLOCK DIAGRAM

REF

POWER-ON

RESET

AD5302/AD5312/AD5322

INPUT

DAC

STRING

DAC

BUFFER

OUT

SYNC

SCLK

DIN

INTERFACE

LOGIC

RESISTOR

NETWORK

POWER-DOWN

LOGIC

INPUT

DAC

STRING

DAC

BUFFER

OUT

RESISTOR

NETWORK

GND

LDAC

REF

*Patent Pending; protected by U.S. Patent No. 5684481.

SPI and QSPI are trademarks of Motorola, Inc.

MICROWIRE is a trademark of National Semiconductor Corporation.

REV. 0

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

Fax: 781/326-8703

World Wide Web Site: http://www.analog.com

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