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AD5301BRT-500RL7 PDF预览

AD5301BRT-500RL7

更新时间: 2024-01-23 16:04:54
品牌 Logo 应用领域
亚德诺 - ADI 转换器数模转换器光电二极管
页数 文件大小 规格书
24页 429K
描述
2.5 V to 5.5 V, 120 μA, 2-Wire Interface, Voltage-Output 8-/10-/12-Bit DACs

AD5301BRT-500RL7 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:SOIC
包装说明:LSSOP,针数:6
Reach Compliance Code:unknown风险等级:5.7
Is Samacsys:N最大模拟输出电压:5.499 V
最小模拟输出电压:0.001 V转换器类型:D/A CONVERTER
输入位码:BINARY输入格式:SERIAL
JESD-30 代码:R-PDSO-G6JESD-609代码:e3
长度:2.9 mm最大线性误差 (EL):0.3906%
湿度敏感等级:1位数:8
功能数量:1端子数量:6
最高工作温度:105 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:LSSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, LOW PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):260认证状态:COMMERCIAL
座面最大高度:1.45 mm标称安定时间 (tstl):6 µs
标称供电电压:3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:MATTE TIN端子形式:GULL WING
端子节距:0.95 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:1.6 mm
Base Number Matches:1

AD5301BRT-500RL7 数据手册

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2.5 V to 5.5 V, 120 μA, 2-Wire Interface,  
Voltage-Output 8-/10-/12-Bit DACs  
AD5301/AD5311/AD5321  
GENERAL DESCRIPTION  
FEATURES  
AD5301: buffered voltage output 8-bit DAC  
AD5311: buffered voltage output 10-bit DAC  
AD5321: buffered voltage output 12-bit DAC  
6-lead SOT-23 and 8-lead MSOP packages  
Micropower operation: 120 μA @ 3 V  
2-wire (I2C®-compatible) serial interface  
Data readback capability  
2.5 V to 5.5 V power supply  
Guaranteed monotonic by design over all codes  
Power-down to 50 nA @ 3 V  
The AD5301/AD5311/AD53211 are single 8-/10-/12-bit, buff-  
ered, voltage-output DACs that operate from a single 2.5 V to  
5.5 V supply, consuming 120 μA at 3 V. The on-chip output  
amplifier allows rail-to-rail output swing with a slew rate of  
0.7 V/μs. It uses a 2-wire (I2C-compatible) serial interface that  
operates at clock rates up to 400 kHz. Multiple devices can share  
the same bus.  
The reference for the DAC is derived from the power supply  
inputs and thus gives the widest dynamic output range. These  
parts incorporate a power-on reset circuit, which ensures that  
the DAC output powers up to 0 V and remains there until a  
valid write takes place. The parts contain a power-down feature  
that reduces the current consumption of the device to 50 nA at  
3 V and provides software-selectable output loads while in  
power-down mode.  
Reference derived from power supply  
Power-on reset to 0 V  
On-chip rail-to-rail output buffer amplifier  
3 power-down functions  
APPLICATIONS  
Portable battery-powered instruments  
Digital gain and offset adjustment  
Programmable voltage and current sources  
Programmable attenuators  
The low power consumption in normal operation makes these  
DACs ideally suited to portable battery-operated equipment. The  
power consumption is 0.75 mW at 5 V and 0.36 mW at 3 V,  
reducing to 1 μW in all power-down modes.  
1 Protected by U.S. Patent No. 5684481.  
FUNCTIONAL BLOCK DIAGRAM  
V
DD  
AD5301/AD5311/AD5321  
SCL  
REF  
SDA  
DAC  
REGISTER  
8-/10-/12-BIT  
DAC  
BUFFER  
V
INTERFACE  
LOGIC  
OUT  
A0  
A1*  
POWER-DOWN  
LOGIC  
RESISTOR  
NETWORK  
POWER-ON  
RESET  
GND  
PD*  
*AVAILABLE ON 8-LEAD VERSION ONLY  
Figure 1.  
Rev. B  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rights of third parties that may result from its use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks and registeredtrademarks arethe property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700 www.analog.com  
Fax: 781.461.3113 ©1999–2007 Analog Devices, Inc. All rights reserved.  
 
 

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