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AD5066BRUZ PDF预览

AD5066BRUZ

更新时间: 2024-02-14 08:36:42
品牌 Logo 应用领域
亚德诺 - ADI 转换器数模转换器光电二极管PC
页数 文件大小 规格书
24页 617K
描述
Fully Accurate, 16-Bit, Unbuffered VOUT, Quad SPI Interface

AD5066BRUZ 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:TSSOP
包装说明:TSSOP,针数:16
Reach Compliance Code:unknown风险等级:5.76
最大模拟输出电压:5.1 V最小模拟输出电压:
转换器类型:D/A CONVERTER输入位码:BINARY
输入格式:SERIALJESD-30 代码:R-PDSO-G16
JESD-609代码:e3长度:5 mm
最大线性误差 (EL):0.0031%湿度敏感等级:1
位数:16功能数量:1
端子数量:16最高工作温度:125 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):225
认证状态:COMMERCIAL座面最大高度:1.2 mm
标称安定时间 (tstl):12 µs表面贴装:YES
温度等级:AUTOMOTIVE端子面层:MATTE TIN
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:4.4 mmBase Number Matches:1

AD5066BRUZ 数据手册

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Fully Accurate, 16-Bit, Unbuffered VOUT, Quad SPI  
Interface, 2.7 V to 5.5 V nanoDAC in a TSSOP  
AD5066  
Total unadjusted error for the part is <0.8 mV. Zero code error  
for the part is 0.05 mV typically.  
FEATURES  
Low power quad 16-bit nanoDAC, 1 LSB INL  
Low total unadjusted error of 0.1 mV typically  
Low zero code error of 0.05 mV typically  
Individually buffered reference pins  
The AD5066 contains a power-down feature that reduces the  
current consumption of the device to typically 400 nA at 5 V  
and provides software selectable output loads while in power-  
down mode.  
2.7 V to 5.5 V power supply  
Specified over full code range of 0 to 65535  
Power-on reset to zero scale or midscale  
Per channel power-down with 3 power-down functions  
The outputs of all DACs can be updated simultaneously using  
LDAC  
the hardware  
user software selectable DAC channels to update simultaneously.  
CLR  
function, with the added functionality of  
Hardware  
with software  
override function  
LDAC  
LDAC  
There is also an asynchronous  
that clears all DACs to a  
function to programmable code  
CLR  
software-selectable code—0 V, midscale, or full scale.  
Small 16-lead TSSOP  
PRODUCT HIGHLIGHTS  
APPLICATIONS  
1. Quad channel available in 16-lead TSSOP, 1 LSB INL.  
2. Individually buffered voltage reference pins.  
3. TUE = 0.8 mV max and zero code error = 0.1 mV max.  
4. High speed serial interface with clock speeds up to 50 MHz.  
5. Three power-down modes available to the user.  
Process control  
Data acquisition systems  
Portable battery-powered instruments  
Digital gain and offset adjustment  
Programmable voltage and current sources  
6. Reset to known output voltage (zero scale or midscale).  
GENERAL DESCRIPTION  
Table 1. Related Devices  
The AD5066 is a low power, 16-bit quad-channel, unbuffered  
voltage output nanoDAC® offering relative accuracy specifica-  
tions of 1 LSB INL with individual reference pins and can  
operate from a single 2.7 V to 5.5 V supply. The AD5066 also  
offers a differential accuracy specification of 1 LSB DNL.  
Reference buffers are also provided on-chip. The part uses a  
versatile 3-wire, low power Schmitt trigger serial interface that  
operates at clock rates up to 50 MHz and is compatible with  
standard SPI®, QSPI™, MICROWIRE™, and most DSP interface  
standards. The AD5066 incorporates a power-on reset circuit  
that ensures the DAC output powers up to zero scale or  
midscale and remains there until a valid write to the device  
takes place.  
Part No.  
Description  
AD5666  
AD5025/AD5045/AD50651  
Quad,16-bit buffered DAC,16 LSB INL, TSSOP  
Dual,12-/14-/16-bit buffered nanoDAC,  
TSSOP  
AD5024/AD5044/AD50641  
AD50621  
AD50631  
AD5061  
AD5040/AD50601  
Quad 16-bit nanoDAC, TSSOP  
Single, 16-bit nanoDAC, SOT-23  
Single, 16-bit nanoDAC, MSOP  
Single,16-bit nanoDAC, 4 LSB INL, SOT-23  
14-/16-bit nanoDAC, SOT-23  
1
1 LSB INL  
FUNCTIONAL BLOCK DIAGRAM  
V
A V  
REF  
B
V
REF  
DD  
AD5066  
LDAC  
INPUT  
REGISTER  
DAC  
REGISTER  
V
A
DAC A  
OUT  
SCLK  
INPUT  
DAC  
V
V
V
B
C
D
DAC B  
DAC C  
OUT  
OUT  
OUT  
REGISTER  
REGISTER  
INTERFACE  
LOGIC  
INPUT  
REGISTER  
DAC  
REGISTER  
SYNC  
DIN  
INPUT  
REGISTER  
DAC  
REGISTER  
DAC D  
POWER-DOWN LOGIC  
POWER-ON RESET  
POR  
V
C V  
REF  
D
GND  
LDAC CLR  
REF  
Figure 1.  
Rev. A  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rightsof third parties that may result fromits use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks andregisteredtrademarks are the property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700 www.analog.com  
Fax: 781.461.3113 ©2009–2010 Analog Devices, Inc. All rights reserved.  
 
 
 
 
 
 

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