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AD5065BRUZ-1REEL7 PDF预览

AD5065BRUZ-1REEL7

更新时间: 2024-02-04 10:50:28
品牌 Logo 应用领域
亚德诺 - ADI 转换器数模转换器光电二极管
页数 文件大小 规格书
33页 755K
描述
Fully Accurate 12-/14-/16-Bit VOUT DAC SPI Interface 2.7 V to 5.5 V in a TSSOP

AD5065BRUZ-1REEL7 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP, TSSOP14,.25针数:14
Reach Compliance Code:compliant风险等级:5.75
Is Samacsys:N最大模拟输出电压:5 V
最小模拟输出电压:转换器类型:D/A CONVERTER
输入位码:BINARY输入格式:SERIAL
JESD-30 代码:R-PDSO-G14JESD-609代码:e3
长度:5 mm最大线性误差 (EL):0.0023%
位数:16功能数量:2
端子数量:14最高工作温度:125 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP14,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):260电源:3/5 V
认证状态:Not Qualified座面最大高度:1.2 mm
标称安定时间 (tstl):14 µs子类别:Other Converters
最大压摆率:4 mA标称供电电压:5 V
表面贴装:YES温度等级:AUTOMOTIVE
端子面层:MATTE TIN端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:4.4 mm
Base Number Matches:1

AD5065BRUZ-1REEL7 数据手册

 浏览型号AD5065BRUZ-1REEL7的Datasheet PDF文件第2页浏览型号AD5065BRUZ-1REEL7的Datasheet PDF文件第3页浏览型号AD5065BRUZ-1REEL7的Datasheet PDF文件第4页浏览型号AD5065BRUZ-1REEL7的Datasheet PDF文件第5页浏览型号AD5065BRUZ-1REEL7的Datasheet PDF文件第6页浏览型号AD5065BRUZ-1REEL7的Datasheet PDF文件第7页 
Fully Accurate 12-/14-/16-Bit VOUT DAC SPI Interface  
2.7 V to 5.5 V in a TSSOP  
Preliminary Technical Data  
AD5025/45/65  
Functional Block Diagrams  
FEATURES  
V
V
V
DD  
REFA  
REFB  
Low power Dual 12-/14-/16 bit DAC, 1LSB INL  
Individual Voltage reference pins  
Rail-to-rail operation  
LDAC  
INPUT  
DAC  
DAC A  
DAC B  
V
A
SCLK  
SYNC  
DIN  
BUFFER  
BUFFER  
OUT  
OUT  
REGISTER  
REGISTER  
INTERFACE  
LOGIC  
2.7 V to 5.5 V power supply  
Power-on reset to zero scale or midscale  
Power down to 400 nA @ 5 V, 200 nA @ 3 V  
3 power-down functions  
INPUT  
REGISTER  
DAC  
REGISTER  
V
B
PDL  
SDO  
AD5025/AD5045R/AD5065  
POWER-ON  
RESET  
POWER-DOWN  
LOGIC  
Per channel power-down  
Low glitch upon power up  
LDAC CLR  
GND  
POR  
Hardware Power Down lock Out Capability  
Hardware LDAC with LDAC override function  
CLR Function to programmable code  
SDO daisy-chaining option  
Figure 1.AD5025/45/65  
Table 1. Related Devices  
14 lead TSSOP  
Part No.  
AD5666  
AD5066  
Description  
Quad,16-bit buffered D/A,16 LSB INL, TSSOP  
Quad,16-bit unbuffered D/A,1 LSB INL, TSSOP  
APPLICATIONS  
AD5064/44/24 Quad 16-bit nanoDAC, 1 LSB INL, TSSOP  
Process control  
AD5063/62  
AD5061  
AD5060/40  
16-bit nanoDAC, 1 LSB INL, MSOP  
16-/14bit nanoDAC, 4 LSB INL, SOT-23  
16-/14bit nanoDAC, 1 LSB INL, SOT-23  
Data acquisition systems  
Portable battery-powered instruments  
Digital gain and offset adjustment  
Programmable voltage and current sources  
Programmable attenuators  
GENERAL DESCRIPTION  
all DACs can be updated simultaneously using the  
function, with the added functionality of user-selectable DAC  
channels to simultaneously update. There is also an  
LDAC  
The AD5025/45/65 are low power, dual 12-/14-/16-bit buffered  
voltage-out DACs offering relative accuracy specs of 1 LSB INL  
with individual reference pins and can operate from a single 2.7  
V to 5.5 V supply. The AD5025/45/65 64 parts also offer a  
differential accuracy specification of 1 LSB. The parts use a  
versatile 3-wire, low power Schmitt trigger serial interface that  
operates at clock rates up to 50 MHz and is compatible with  
standard SPI®, QSPI™, MICROWIRE™, and DSP interface  
standards. The reference for the AD5025/45 and AD5065 are  
supplied from an external pin. A reference buffer is also  
provided on-chip. The AD5025/45/64 incorporates a power-on  
reset circuit that ensures the DAC output powers up zero scale  
or midscale and remains there until a valid write takes place to  
the device. The AD5025/45/65 contain a power-down feature  
that reduces the current consumption of the device to typically  
330 nA at 5 V and provides software selectable output loads  
while in power-down mode. The parts are put into power-down  
mode over the serial interface. Total unadjusted error for the  
parts is <2 mV.  
asynchronous  
that clears all DACs to a software-selectable  
CLR  
code—0 V, midscale, or full scale. The Part also features a power  
down lockout pin , which can be used to prevent the DAC  
PDL  
from entering power down under any circumstances over the  
serial interface.  
PRODUCT HIGHLIGHTS  
1. Dual channel available in 14-lead TSSOP package with  
individual Voltage reference pins.  
2. 12-/14-/-16 bit accurate, 1 LSB INL.  
3. Low glitch on power-up.  
4. High speed serial interface with clock speeds up to 50 MHz.  
5. Three power-down modes available to the user.  
6. Reset to known output voltage (zero scale or midscale).  
7. Power Down lockout capability.  
Both parts exhibit very low glitch on power-up. The outputs of  
Rev. PrB  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rights of third parties that may result from its use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks and registeredtrademarks arethe property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Fax: 781.461.3113  
www.analog.com  
© 2007 Analog Devices, Inc. All rights reserved.  

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