GSM
a
Baseband Processing Chipset
AD20msp410
SYSTEM ARCH ITECTURE
FEATURES
Passed European GSM Phase I Type Approval
Com plete Baseband Processing Chipset Perform s:
Speech Coding/ Decoding, According to GSM 06.XX
DTMF and Call Progress Tone Generation
Equalization w ith 16-State Viterbi, Soft Decision
Channel Coding/ Decoding According to GSM 05.03
All ADC and DAC Interface Functions
Includes all Radio, Auxiliary and Voice Interfaces
Support for GSM Data Services
ALGORITHM
BASEBAND
SIGNAL
CONVERTER
PROCESSOR
RADIO
SUBSYSTEM
BBC
ASP
PHYSICAL
LAYER
PROCESSOR
PLP
µC
Em bedded 16-Bit Microcontroller
AD20msp410
GSM CHIPSET
Layer 1 Softw are Provided w ith Chipset
Full Phase 2 Protocol Stack Softw are Available
Integrated SIM- and Keyboard Interface
Ultralow Pow er Design
2.7 V Operating Voltage
Intelligent Pow er Managem ent Features
Up to 70 Hours Standby Tim e Achievable
J TAG-Boundary Scan
512K x 16
ROM
128K x 8
RAM
2K x 8
EEPROM
DISPLAY
KEYPAD
SIM
Full Reference Design Available
Three TQFP Devices, Occupying Less than 12 cm 2
APPLICATIONS
GSM/ DCS1800 Mobile Radios and PCMCIA Cards
GENERAL D ESCRIP TIO N
preprogrammed ROM, no user programming is required. T he
ASP implements full rate speech transcoding according to GSM
specifications, including Discontinuous T ransmission (DT X)
and Comfort Noise Insertion (CNI). A high performance soft-
decision Viterbi equalizer is also implemented in software,
embedded in the ROM.
T he Analog Devices GSM baseband processing chipset provides
a competitive solution for GSM based mobile radio systems. It
is designed to be fully integrated, easy to use, and compatible
with a wide range of product solutions. GSM phones using this
chipset and its accompanying Layer 1, 2, 3 software have passed
the European GSM full type approval process.
P hysical Layer P r ocessor (P LP )
T he chipset consists of three highly integrated, sub-micron, low
power CMOS components that form the core baseband signal
processing of the GSM handset. T he system architecture is
designed to be easily integrated into current designs and form
the basis of next generation of designs.
T he PLP combines application specific hardware and an
embedded 16-bit microcontroller (H itachi H 8/300H ) to
perform channel coding and decoding and execute the protocol
stack and user software. T he embedded processor executes the
Layer 1, 2, 3 and user MMI software. T he PLP can control all
powerdown functions of the other chips and memory support
components to achieve maximum power savings.
T he chipset uses an operating voltage of 2.7 V to 3.6 V, which
coupled with the extensive power management features,
significantly reduces the drain on battery power and extends the
handset’s talktime and standby time.
Baseband Conver ter (BBC)
T he BBC performs the voiceband and baseband analog-to-
digital and digital-to-analog conversions, interfacing the digital
sections of the chipset to the microphone, loudspeaker and radio
section. In addition, the BBC contains all the auxiliary convert-
ers for burst-ramping, AFC, AGC, battery and temperature
monitoring. T he chipset interfaces directly with a variety of
industry standard radio architectures and supplies all the
synthesizer and timing control signals.
CH IP SET CO MP O NENTS
Algor ithm Signal P r ocessor (ASP )
T he ASP is an application specific variant of the ADSP-2171
standard DSP from Analog Devices. It has been optimized to
meet the cost, size and power consumption requirements of
GSM mobile applications. All necessary memory to run the
GSM specific programs is provided on-chip and with its
REV. 0
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
© Analog Devices, Inc., 1996
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 617/ 329-4700
Fax: 617/ 326-8703
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