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AD1937WBSTZ-RL PDF预览

AD1937WBSTZ-RL

更新时间: 2024-02-22 04:44:32
品牌 Logo 应用领域
亚德诺 - ADI 解码器转换器数模转换器编解码器
页数 文件大小 规格书
36页 581K
描述
Four ADCs/Eight DACs with PLL, 192 kHz, 24-Bit Codec

AD1937WBSTZ-RL 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Obsolete零件包装代码:QFP
包装说明:LFQFP,针数:64
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.79
Is Samacsys:N其他特性:WITH PROGRAMMABLE PLL
转换器类型:D/A CONVERTER输入位码:BINARY
输入格式:SERIALJESD-30 代码:S-XQFP-G64
长度:10 mm功能数量:8
端子数量:64最高工作温度:105 °C
最低工作温度:-40 °C封装主体材料:UNSPECIFIED
封装代码:LFQFP封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE, FINE PITCH峰值回流温度(摄氏度):NOT SPECIFIED
认证状态:Not Qualified座面最大高度:1.6 mm
标称供电电压:3.3 V表面贴装:YES
温度等级:INDUSTRIAL端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:10 mm
Base Number Matches:1

AD1937WBSTZ-RL 数据手册

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Four ADCs/Eight DACs with PLL,  
192 kHz, 24-Bit Codec  
AD1937  
GENERAL DESCRIPTION  
FEATURES  
The AD1937 is a high performance, single-chip codec that provides  
four analog-to-digital converters (ADCs) with differential input  
and eight digital-to-analog converters (DACs) with differential  
output, using the Analog Devices, Inc., patented multibit sigma-  
delta (Σ-Δ) architecture. An I2C® port is included, allowing a  
microcontroller to adjust volume and many other parameters.  
The AD1937 operates from 3.3 V digital and analog supplies.  
The AD1937 is available in a 64-lead (differential output) LQFP.  
PLL-generated clock or direct master clock  
Low EMI design  
112 dB DAC/107 dB ADC dynamic range and SNR  
−96 dB THD + N  
Single 3.3 V supply  
Tolerance for 5 V logic inputs  
Supports 24-bits and 8 kHz to 192 kHz sample rates  
Differential ADC input  
Differential DAC output  
Log volume control with autoramp function  
I2C-controllable for flexibility  
Software-controllable clickless mute  
Software power-down  
Right-justified, left-justified, I2S, and TDM modes  
Master and slave modes up to 16-channel input/output  
Available in a 64-lead LQFP  
The AD1937 is designed for low EMI. This consideration is  
apparent in both the system and circuit design architectures.  
By using the on-board PLL to derive the master clock from the  
LR (frame) clock or from an external crystal, the AD1937 elimi-  
nates the need for a separate high frequency master clock and  
can also be used with a suppressed bit clock. The DACs and  
ADCs are designed using the latest Analog Devices continuous  
time architecture to further minimize EMI. By using 3.3 V  
supplies, power consumption is minimized and further  
reduces emissions.  
AECQ-100 qualified  
APPLICATIONS  
Automotive audio systems  
Home theater systems  
Set-top boxes  
Digital audio effects processors  
FUNCTIONAL BLOCK DIAGRAM  
DIGITAL AUDIO  
INPUT/OUTPUT  
AD1937  
SERIAL DATA PORT  
DAC  
DAC  
DAC  
DAC  
DAC  
DAC  
DAC  
DAC  
SDATA  
OUT  
SDATA  
IN  
ADC  
ADC  
ADC  
ADC  
DIGITAL  
FILTER  
AND  
VOLUME  
CONTROL  
ANALOG  
AUDIO  
INPUTS  
CLOCKS  
ANALOG  
AUDIO  
OUTPUTS  
DIGITAL  
FILTER  
TIMING MANAGEMENT  
AND CONTROL  
(CLOCK AND PLL)  
2
I C  
PRECISION  
VOLTAGE  
REFERENCE  
CONTROL PORT  
CONTROL DATA  
INPUT/OUTPUT  
Figure 1.  
Rev. 0  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rights of third parties that may result from its use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks and registeredtrademarks arethe property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Fax: 781.461.3113  
www.analog.com  
©2008 Analog Devices, Inc. All rights reserved.  
 
 
 

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