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ACS760ELF-20BTR-T

更新时间： 2024-09-17 04:03:31
品牌 Logo 应用领域
急速微 - ALLEGRO 模拟IC信号电路监视器光电二极管
页数 文件大小 规格书
15页 785K
描述
12 V High-Side Hot-Swap Hall Effect Based Current Monitor

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ACS760ELF-20BTR-T 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：SSOP包装说明：SSOP, SSOP24,.24
针数：24Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.6
Is Samacsys：N模拟集成电路 - 其他类型：ANALOG CIRCUIT
JESD-30 代码：R-PDSO-G24JESD-609代码：e3
长度：8.65 mm功能数量：1
端子数量：24最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：SSOP封装等效代码：SSOP24,.24
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, SHRINK PITCH
峰值回流温度（摄氏度）：260电源：12 V
认证状态：Not Qualified座面最大高度：1.75 mm
子类别：Power Management Circuits最大供电电流 (Isup)：12 mA
最大供电电压 (Vsup)：13.2 V最小供电电压 (Vsup)：10.8 V
标称供电电压 (Vsup)：12 V表面贴装：YES
温度等级：INDUSTRIAL端子面层：Matte Tin (Sn)
端子形式：GULL WING端子节距：0.635 mm
端子位置：DUAL处于峰值回流温度下的最长时间：40
宽度：3.9 mmBase Number Matches：1

ACS760ELF-20BTR-T 数据手册

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ACS760ELF-20B  
12 V High-Side Hot-Swap Hall Effect Based Current Monitor  
Features and Benefits  
Description  
▪ Hall-effect current monitor—no external sense resistor required  
▪ Analog output voltage (factory trimmed for gain and  
offset) proportional to applied current  
The ACS760 combines Allegro® Hall-effect current sense  
technology with a hot-swap controller resulting in a more  
efficient integrated controller for 12 V applications. By  
eliminating the need for a shunt resistor, the I2R losses in the  
power path are reduced.  
▪ External high-side FET gate drive  
▪ 240V*A Power Fault Protection with user-programmable delay  
▪ User programmable Overcurrent Fault Protection with  
programmable delay  
▪ 1.5 mΩ internal conductor resistance  
▪ Short Circuit Protection isolates failed supply from  
output in < 2 μs  
▪ Active low Fault indicator output signal  
▪ External FET failure detection with active low S1 Short  
failure indicator output signal  
▪ User controlled soft start / hot-swap function  
▪ Logic enable input pin  
When theACS760 is externally enabled, and the voltage rail is  
above the internal UVLO threshold, the internal charge pump  
drivesthegateoftheexternalFET.Whenafaultisdetected,the  
gate is disabled while simultaneously alerting the application  
that a fault has occurred.  
The integrated protection in the ACS760 incorporates three  
levels of fault protection, which includes a Power Fault with  
user-programmable delay, a user-programmable Overcurrent  
Fault threshold with programmable delay, and Short Circuit  
protection, which disables the gate in less then 2 μs.  
▪ 10.8 to 13.2 V, single-supply operation  
▪ 2 kV ESD protection for all pins  
Additionally, in the event the external high-side FET fails  
short,theACS760detectstheS1Shortfailureandimmediately  
disables the gate and alerts the host system. Unlike the three  
protectionfaults, cyclingtheENpindoesnotresettheS1Short  
failure. Power to the device must be cycled.  
Package: 24 pin QSOP (suffix LF)  
Approximate Scale  
Typical Application  
Backplane  
IP  
VS_IN  
24  
IP–  
1
2
3
4
5
6
7
8
9
RV1  
A
CIN  
IP+  
23  
IP+  
IP–  
S1  
RG  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
VLOAD  
IP+  
IP–  
IP–  
VS_RET  
Enable  
IP+  
ACS760  
IP+  
IP–  
REN  
CEN  
CLOAD  
D1  
B
IP+  
IP–  
RFB  
EN  
GATE  
GND  
VOUT  
VIOUT  
ISET  
CG  
3.3 V  
FB–  
C
RSET  
10  
11  
12  
RS1  
RFAULT  
FB+  
CG  
COCD  
COPD  
OCDLY  
OPDLY  
S1SHORT  
FAULT  
A
B
C
RV1 is required only for inductive loads.  
D1 should be a Schottky for inductive loads, to eliminate over-stress of the ACS760.  
FB– is tied to GND at the point of load.  
760ELF20B-DS, Rev. 2  
1234567...15

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