ABX2005/06/07/08/09
Low Phase Noise XO with multipliers (for 100-200MHz Fund or 3rdOT Xtal)
Universal Low Phase Noise IC’s
FEATURES
PIN CONFIGURATION
(Top View)
•
•
100MHz to 200MHz Fundamental or 3rd
Overtone Crystal.
Output range: 100 – 200MHz (no multiplication),
200 – 400MHz (2x multiplier), 400 – 700MHz (4x
multiplier), or 800MHz-1GHz(ABX2009 only, 8x
multiplier).
CMOS (Standard drive ABX2007 or Selectable
Drive ABX2006), PECL (Enable low ABX2008 or
Enable high ABX2005) or LVDS output
(ABX2009).
1
VDD
XIN
1
2
3
4
5
6
7
8
SEL0^
SEL1^
GND
6
1
5
1
4
1
3
1
2
1
XOUT
SEL3^
SEL2^
OE
•
CLKC
VDD
CLKT
GND
1
1
0
•
•
Supports 3.3V-Power Supply.
GND
GND
Available in 16-Pin (TSSOP or 3x3mm QFN)
Note: ABX2006 only available in 3x3mm.
Note: ABX2007 only available in TSSOP.
9
GND
DESCRIPTION
The ABX200x family of XO IC’s is specifically
designed to work with high frequency fundamental
and third overtone crystals. Their low jitter and low
phase noise performance make them well suited for
high frequency XO requirements. They achieve very
low current into the crystal resulting in better overall
stability.
12
11
10
9
13
14
15
8
7
6
5
XIN
GND
CLKC
VDD
XOUT
SEL2^
ABX200x
16
CLKT
OE
1
2
3
4
^: Internal pull-up
*: ABX2006 pin 12 is output drive select (DRIVSEL)
(0 for High Drive CMOS, 1 for Standard Drive CMOS)
BLOCK DIAGRAM
SEL
OE
OUTPUT ENABLE LOGICAL LEVELS
PLL
(Phase
Q
Part #
OE
0
State
Locked
Loop)
Q
Oscillator
Amplifier
Output enabled
(Default)
ABX2008
X+
X-
1
0
Tri-state
Tri-state
ABX2005
ABX2006
ABX2007
ABX2009
PLL by-pass
1
Output enabled
(Default)
OE input: Logical states defined by PECL levels for ABX2008
Logical states defined by CMOS levels for
ABX2005/06/07/09
30332 Esperanza., Rancho Santa Margarita, Ca 92688 Ph: 949-546-8000 Fax: 949-546-8001 www.Abracon.com 03/21/05 Page 1