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AP P LICATION BULLETIN
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DDC101 EVALUATION FIXTURE PC INTERFACE BOARD
By Timothy V. Kalthoff
The DDC101 Evaluation Fixture is a modular design. With
the use of the common DDC101 Evaluation Fixture PC
Interface Board, different Device Under Test (DUT) Boards
may be used. Different DUT boards can be used to evaluate
single or up to 32 DDC101s in any package type. Design of
the DUT boards and their use are detailed in the DDC101
Evaluation Fixture product data sheet.
LOCATING THE PC’S PARALLEL
PORT’S ADDRESS
1
The PC interface board receives its instructions via the PC’s
parallel port. The address for the parallel printer port is
found by reading it from the BIOS memory. LPT1, printer
port 1’s address, is located at hexidecimal address 40H, 08H
(segment, offset). LPT2, printer port 2’s address, is located
at hexidecimal address 40H, 0AH.
3
4
This application note focuses on how to communicate di-
rectly to the PC Interface Board through a PC’s printer port.
This communication is used to configure the PC Interface
Board as well as to configure and retrieve data from the
DDC101s on the DUT Board. This will allow the user to
write custom software to create user specific, extended
capabilities not available in the standard program.
ACCESSING THE PC INTERFACE
BOARD REGISTERS
When information is sent to the PC Interface Board from the
PC, bit 7 of the PC’s Parallel Output Port is used to
determine whether it is a register address or data to be
written into a register. To write to a register, first send the
register address with bit 7 low. This enables only the desired
register to be written to. Then send the data with bit 7 high.
5
6
The software for the DDC101 Evaluation Board was written
in Turbo Pascal®. The code can be readily modified to be
used with other languages. All software examples listed use
Turbo Pascal syntax.
Note, whenever data is sent to the PC Interface Board (bit 7
high) the last register addressed will be written to. It is
recommended that prior to transmitting each register’s data,
first send the register’s address.
DDC101 EVALUATION FIXTURE—
PC INTERFACE BOARD
The DDC101 Evaluation Fixture’s PC Interface Board is a
data collection board designed to provide full operational
control of the DDC101. The PC Interface Board provides
control signals for the DDC101 and can collect up to 32,768
data words of DDC101 serial output. The PC Interface
Board provides computer communication via the parallel
interface port of an IBM compatible PC. The board can be
used to evaluated up to 32 multiple DDC101s with their
control signals connected in parallel and their outputs/inputs
serially connected.
Table I lists the addresses of the registers which are con-
tained in the PC Interface Board. Table II provides a descrip-
tion of these registers.
INITIALIZATION
The DDC101 PC Interface Board contains seven registers
which must be initialized to establish control and timing for
the DDC101 under test (refer to Table I and II). These
registers control: Data Clock Rate, System Clock Rate,
Integration Time, Data Transfer Delay, Number of DDC101s,
DDC101 Setup Configuration, and PC Interface Board data
collection.
Control of the DDC101 from the PC is attained by loading
control data into the PC Interface Board’s registers. These
registers are used for controlling system and data clock rates,
integration time, number of DDC101’s, readback delay, and
the mode of operation. The following contains procedures
for setting up the DDC101, collecting data from the DDC101
and writing to the on board RAM, and reading back the data
from RAM.
DDC101 DATA COLLECTION MODE
Bit 5 of the Control Register determines the data transfer
mode the DDC101 Evaluation Fixture will be in. The data is
either being collected from the DDC101 under test and
stored into the PC Interface Board’s RAM or the data is
being retrieved from the RAM and read back to the PC.
PC INTERFACE BOARD SCHEMATICS
Data Storage—Setting bit 5 of the Control Register high
initiates the data collect function of the PC Interface Board.
At the end of each DDC101 conversion, Data Valid becomes
active. Upon receipt of Data Valid, the PC Interface Board
The PC Interface Board schematic is shown in Figure 1. The
PC Interface Board uses two Xilinx Field Programmable
Logic Arrays. The schematics for these are shown in Figures
2-8. For completeness, a single DDC101 DUT board sche-
matic is shown in Figure 9.
Turbo Pascal®, Borland International, Inc.
©1994 Burr-Brown Corporation
AB-097
Printed in U.S.A. November, 1994
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