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A80960CA-33 PDF预览

A80960CA-33

更新时间: 2024-01-26 00:30:53
品牌 Logo 应用领域
英特尔 - INTEL 时钟外围集成电路装置
页数 文件大小 规格书
68页 960K
描述
RISC Microprocessor, 32-Bit, 33MHz, MOS, CPGA168, CERAMIC, PGA-168

A80960CA-33 技术参数

生命周期:Obsolete零件包装代码:PGA
包装说明:CERAMIC, PGA-168针数:168
Reach Compliance Code:unknownECCN代码:3A001.A.3
HTS代码:8542.31.00.01风险等级:5.79
其他特性:OPERATING CASE TEMPERATURE 0 TO 100 C地址总线宽度:32
位大小:32边界扫描:NO
最大时钟频率:66.66 MHz外部数据总线宽度:32
格式:FIXED POINT集成缓存:NO
JESD-30 代码:S-CPGA-P168长度:44.7 mm
低功率模式:NODMA 通道数量:4
外部中断装置数量:9串行 I/O 数:
端子数量:168片上数据RAM宽度:8
最高工作温度:100 °C最低工作温度:
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:PGA
封装等效代码:PGA168,17X17封装形状:SQUARE
封装形式:GRID ARRAY电源:5 V
认证状态:Not QualifiedRAM(字数):512
座面最大高度:4.57 mm速度:33 MHz
子类别:Microprocessors最大压摆率:900 mA
最大供电电压:5.25 V最小供电电压:4.75 V
标称供电电压:5 V表面贴装:NO
技术:MOS温度等级:OTHER
端子形式:PIN/PEG端子节距:2.54 mm
端子位置:PERPENDICULAR宽度:44.7 mm
uPs/uCs/外围集成电路类型:MICROPROCESSOR, RISCBase Number Matches:1

A80960CA-33 数据手册

 浏览型号A80960CA-33的Datasheet PDF文件第2页浏览型号A80960CA-33的Datasheet PDF文件第3页浏览型号A80960CA-33的Datasheet PDF文件第4页浏览型号A80960CA-33的Datasheet PDF文件第5页浏览型号A80960CA-33的Datasheet PDF文件第6页浏览型号A80960CA-33的Datasheet PDF文件第7页 
80960CA-33, -25, -16  
32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR  
• Two Instructions/Clock Sustained Execution  
• Four 59 Mbytes/s DMA Channels with Data Chaining  
• Demultiplexed 32-bit Burst Bus with Pipelining  
32-bit Parallel Architecture  
— Two Instructions/clock Execution  
— Load/Store Architecture  
Four On-Chip DMA Channels  
— 59 Mbytes/s Fly-by Transfers  
— 32 Mbytes/s Two-Cycle Transfers  
— Data Chaining  
— Sixteen 32-bit Global Registers  
— Sixteen 32-bit Local Registers  
— Manipulates 64-bit Bit Fields  
— 11 Addressing Modes  
— Full Parallel Fault Model  
— Supervisor Protection Model  
— Data Packing/Unpacking  
— Programmable Priority Method  
32-Bit Demultiplexed Burst Bus  
— 128-bit Internal Data Paths to and  
from Registers  
Fast Procedure Call/Return Model  
— Burst Bus for DRAM Interfacing  
— Address Pipelining Option  
— Fully Programmable Wait States  
— Supports 8-, 16- or 32-bit Bus Widths  
— Supports Unaligned Accesses  
— Supervisor Protection Pin  
— Full Procedure Call in 4 Clocks  
On-Chip Register Cache  
— Caches Registers on Call/Ret  
— Minimum of 6 Frames Provided  
— Up to 15 Programmable Frames  
Selectable Big or Little Endian Byte  
On-Chip Instruction Cache  
— 1 Kbyte Two-Way Set Associative  
— 128-bit Path to Instruction Sequencer  
— Cache-Lock Modes  
Ordering  
High-Speed Interrupt Controller  
— Up to 248 External Interrupts  
— 32 Fully Programmable Priorities  
— Multi-mode 8-bit Interrupt Port  
— Four Internal DMA Interrupts  
— Separate, Non-maskable Interrupt Pin  
— Context Switch in 750 ns Typical  
— Cache-Off Mode  
High Bandwidth On-Chip Data RAM  
— 1 Kbyte On-Chip Data RAM  
— Sustains 128 bits per Clock Access  
Intel Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in an Intel product. No other circuit patent  
licenses are implied. Information contained herein supersedes previously published specifications on these devices from Intel.  
© INTEL CORPORATION, 1993  
November 1993  
Order Number: 270727-006  

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