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A6801SLWTR-T

更新时间： 2024-11-18 13:00:11
品牌 Logo 应用领域
急速微 - ALLEGRO 驱动器
页数 文件大小 规格书
12页 435K
描述
Latch Based Peripheral Driver, 1 Driver, BICMOS, PDSO24, LEAD FREE, MS-013AD, SOIC-24

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中文翻译

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A6801SLWTR-T 技术参数

是否Rohs认证：符合生命周期：Obsolete
零件包装代码：SOIC包装说明：LEAD FREE, MS-013AD, SOIC-24
针数：24Reach Compliance Code：unknown
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.68Is Samacsys：N
内置保护：TRANSIENT驱动器位数：1
接口集成电路类型：LATCH BASED PERIPHERAL DRIVERJESD-30 代码：R-PDSO-G24
JESD-609代码：e3长度：15.4 mm
湿度敏感等级：3功能数量：1
端子数量：24最高工作温度：85 °C
最低工作温度：-20 °C输出电流流向：SINK
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：SOP24,.4封装形状：RECTANGULAR
封装形式：SMALL OUTLINE电源：3.3/5 V
认证状态：Not Qualified座面最大高度：2.65 mm
子类别：Peripheral Drivers最大供电电压：5.5 V
最小供电电压：3 V标称供电电压：3.3 V
表面贴装：YES技术：BICMOS
温度等级：OTHER端子面层：Matte Tin (Sn)
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL宽度：7.5 mm
Base Number Matches：1

A6801SLWTR-T 数据手册

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A6800/A6801  
DABiC-5 Latched Sink Drivers  
The A6800 and A6801 latched-input BiMOS ICs merge high-current,  
high-voltage outputs with CMOS logic. The CMOS input section con-  
sists of 4 or 8 data (‘D’ type) latches with associated common CLEAR,  
STROBE, and OUTPUT ENABLE circuitry. The power outputs are  
bipolar NPN Darlingtons. This merged technology provides versatile,  
flexible interface. These BiMOS power interface ICs greatly benefit the  
simplification of computer or microprocessor I/O. The A6800 ICs each  
contain four latched drivers. A6801 ICs contain eight latched drivers.  
A6800SA  
A6800SL  
The CMOS inputs are compatible with standard CMOS circuits. TTL  
circuits may mandate the addition of input pull-up resistors. The bipolar  
Darlington outputs are suitable for directly driving many peripheral/  
power loads: relays, lamps, solenoids, small dc motors, etc.  
All devices have open-collector outputs and integral diodes for induc-  
tive load transient suppression. The output transistors are capable of  
sinking 600 mA and will withstand at least 50 V in the OFF state.  
Because of limitations on package power dissipation, the simultaneous  
operation of all drivers at maximum rated current can only be accom-  
plished by a reduction in duty cycle. Outputs may be paralleled for  
higher load current capability.  
A6801SA  
A6801SEP  
The A6800SA is furnished in a standard 14-pin DIP; the A6800SL and  
A6801SLW in surface-mountable SOICs; the A6801SA in a 22-pin  
DIP with 0.400” (10.16 mm) row centers; the A6801SEP in a 28-lead  
PLCC. These devices are lead (Pb) free, with 100% matte tin plated  
leadframes.  
A6801SLW  
ABSOLUTE MAXIMUM RATINGS  
FEATURES  
„
„
„
„
3.3 V to 5Vlogic supply range  
„
„
„
„
CMOS, TTL compatible inputs  
Output transient protection  
Internal pull-down resistors  
Low-power CMOS latches  
Output Voltage, VCE............................................50 V  
Supply Voltage, VDD.............................................7 V  
Input Voltage Range,VIN ..............–0.3VtoVDD +0.3V  
Continuous Collector Current, IC........................ 600 mA  
Package Power Dissipation, PD, see Allowable Power  
Disspation chart, page 5  
To 10 MHz data input rate  
High-voltage, high-current outputs  
Darlington current-sink outputs, with  
improved low-saturation voltages  
APPLICATIONS  
Operating Temperature Range  
„
„
Solenoids  
Small dc motors  
„
„
Relays  
Lamps  
Ambient Temperature, TA............–20°C to +85°C  
Storage Temperature, TS ..........–55°C to +150°C  
Use the following complete part numbers when ordering:  
Part Number  
A6800SA-T  
A6800SL-T  
A6801SA-T  
A6801SEP-T  
A6801SLW-T  
Pins  
14  
Package  
DIP  
Caution: CMOS devices have input-static protection,  
but are susceptible to damage when exposed to  
extremely high static-electrical charges.  
14  
SOIC  
DIP  
22  
28  
PLCC  
SOIC  
24  
1234567...12

中文翻译

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A6801SLWTR-T 替代型号

型号 品牌 替代类型 描述 数据表
A6801SLW-T ALLEGRO

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