Datasheet > A3P250-PQG208

A3P250-PQG208

更新时间： 2024-11-09 20:34:35

品牌	Logo	应用领域
ACTEL		栅可编程逻辑
页数	文件大小	规格书
218页	6270K
描述
Field Programmable Gate Array, 250000 Gates, CMOS, PQFP208, 0.50 MM PITCH, PLASTIC, QFP-208

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技术参数
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A3P250-PQG208 技术参数

是否Rohs认证：	符合	生命周期：	Transferred
包装说明：	0.50 MM PITCH, PLASTIC, QFP-208	Reach Compliance Code：	unknown
风险等级：	5.75	Is Samacsys：	N
JESD-30 代码：	S-PQFP-G208	长度：	28 mm
等效关口数量：	250000	端子数量：	208
最高工作温度：	70 °C	最低工作温度：
组织：	250000 GATES	封装主体材料：	PLASTIC/EPOXY
封装代码：	FQFP	封装形状：	SQUARE
封装形式：	FLATPACK, FINE PITCH	峰值回流温度（摄氏度）：	NOT SPECIFIED
可编程逻辑类型：	FIELD PROGRAMMABLE GATE ARRAY	认证状态：	Not Qualified
座面最大高度：	4.1 mm	最大供电电压：	1.575 V
最小供电电压：	1.425 V	标称供电电压：	1.5 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子形式：	GULL WING
端子节距：	0.5 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	28 mm
Base Number Matches：	1

A3P250-PQG208 数据手册

v1.3

ProASIC3 Flash Family FPGAs

with Optional Soft ARM Support

• Wide Range Power Supply Voltage Support per JESD8-B,

Allowing I/Os to Operate from 2.7 V to 3.6 V

Features and Benefits

• 15 k to 1 M System Gates

• Up to 144 kbits of True Dual-Port SRAM

• Up to 300 User I/Os

High Capacity

• Bank-Selectable I/O Voltages—up to 4 Banks per Chip

• Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /

†

2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X and LVCMOS

2.5 V / 5.0 V Input

• Differential I/O Standards: LVPECL, LVDS, B-LVDS, and

M-LVDS (A3P250 and above)

Reprogrammable Flash Technology

• 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process

• Live at Power-Up (LAPU) Level 0 Support

• Single-Chip Solution

• I/O Registers on Input, Output, and Enable Paths

‡

• Hot-Swappable and Cold Sparing I/Os

†

• Programmable Output Slew Rate and Drive Strength

• Retains Programmed Design when Powered Off

High Performance

• Weak Pull-Up/-Down

• IEEE 1149.1 (JTAG) Boundary Scan Test

• Pin-Compatible Packages across the ProASIC3 Family

Clock Conditioning Circuit (CCC) and PLL^†

• Six CCC Blocks, One with an Integrated PLL

• 350 MHz System Performance

†

• 3.3 V, 66 MHz 64-Bit PCI

In-System Programming (ISP) and Security

• Secure ISP Using On-Chip 128-Bit Advanced Encryption

• Configurable

Phase-Shift,

Multiply/Divide,

Delay

Standard (AES) Decryption (except ARM-enabled ProASIC 3

†

Capabilities and External Feedback

• Wide Input Frequency Range (1.5 MHz to 350 MHz)

Embedded Memory^†

devices) via JTAG (IEEE 1532–compliant)

• FlashLock to Secure FPGA Contents

Low Power

• 1 kbit of FlashROM User Nonvolatile Memory

• Core Voltage for Low Power

• SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM

• Support for 1.5 V-Only Systems

†

Blocks (×1, ×2, ×4, ×9, and ×18 organizations)

• Low-Impedance Flash Switches

• True Dual-Port SRAM (except ×18)

High-Performance Routing Hierarchy

• Segmented, Hierarchical Routing and Clock Structure

Advanced I/O

ARM Processor Support in ProASIC3 FPGAs

• M1 ProASIC3 Devices—ARM Cortex™-M1 Soft Processor

Available with or without Debug

• 700 Mbps DDR, LVDS-Capable I/Os (A3P250 and above)

• 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation

Table 1 • ProASIC3 Product Family

ProASIC3 Devices

Cortex-M1 Devices

System Gates

A3P015

A3P030

A3P060 A3P125

A3P250

A3P400

A3P600

A3P1000

M1A3P250 M1A3P400

M1A3P600 M1A3P1000

15 k

128

384

–

30 k

256

768

–

60 k

512

1,536

125 k

1,024

3,072

250 k

2,048

6,144

400 k

–

600 k

–

1 M

–

Typical Equivalent Macrocells

VersaTiles (D-flip-flops)

RAM kbits (1,024 bits)

4,608-Bit Blocks

9,216

13,824

108

24,576

144

–

FlashROM Bits

1 k

–

1 k

–

1 k

Yes

1 k

Yes

1 k

Yes

1 k

Yes

1 k

Yes

1 k

Yes

Secure (AES) ISP

Integrated PLL in CCCs

–

VersaNet Globals

I/O Banks

Maximum User I/Os

133

157

194

235

300

Package Pins

QFN

QN68

QN48, QN68,

QN132

CS121

VQ100

TQ144

VQFP

TQFP

PQFP

FBGA

VQ100

TQ144

PQ208

VQ100

PQ208

FG144

FG144 FG144/256

FG144/256/ FG144/256/ FG144/256/

484

Notes:

1. Refer to the Cortex-M1 product brief for more information.

2. AES is not available for ARM-enabled ProASIC3 devices.

3. Six chip (main) and three quadrant global networks are available for A3P060 and above.

4. For higher densities and support of additional features, refer to the ProASIC3E Flash Family FPGAs handbook.

5. The M1A3P250 device does not support this package.

†

A3P015 and A3P030 devices do not support this feature.

‡ Supported only by A3P015 and A3P030 devices.

October 2009

12 3 4 5 6 7...218

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与A3P250-PQG208相关器件

型号	品牌	获取价格	描述	数据表
A3P250-PQG208I	ACTEL	获取价格	Field Programmable Gate Array, 250000 Gates, CMOS, PQFP208, 0.50 MM PITCH, GREEN, PLASTIC,
A3P250-PQG208I	MICROSEMI	获取价格	暂无描述
A3P250-PQG208II	MICROSEMI	获取价格	FPGA, 6144 CLBS, 250000 GATES, 350MHz, PQFP208, 28 X 28 MM, 3.40 MM HEIGHT, 0.50 MM PITCH,
A3P250-PQG208IY	MICROSEMI	获取价格	Field Programmable Gate Array,
A3P250-PQG208Y	MICROSEMI	获取价格	Field Programmable Gate Array, 6144 CLBs, 250000 Gates, CMOS, PQFP208, 28 X 28 MM, 3.40 MM
A3P250-PQG208YI	MICROSEMI	获取价格	Field Programmable Gate Array, 6144 CLBs, 250000 Gates, CMOS, PQFP208, 28 X 28 MM, 3.40 MM
A3P250-QN100	MICROSEMI	获取价格	ProASIC3 Flash Family FPGAs with Optional Soft ARM Support
A3P250-QN100ES	MICROSEMI	获取价格	ProASIC3 Flash Family FPGAs with Optional Soft ARM Support
A3P250-QN100I	MICROSEMI	获取价格	ProASIC3 Flash Family FPGAs with Optional Soft ARM Support
A3P250-QN100PP	MICROSEMI	获取价格	ProASIC3 Flash Family FPGAs with Optional Soft ARM Support

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