5秒后页面跳转
捷配首页

Datasheet > A3P250-PQ208IY
A3P250-PQ208IY PDF预览

A3P250-PQ208IY

更新时间： 2024-11-07 03:30:15
品牌 Logo 应用领域
美高森美 - MICROSEMI 栅可编程逻辑
页数 文件大小 规格书
221页 6478K
描述
Field Programmable Gate Array,

阅读下载

中文翻译

获取价格

A3P250-PQ208IY 技术参数

生命周期：Active包装说明：,
Reach Compliance Code：compliant风险等级：5.2
可编程逻辑类型：FIELD PROGRAMMABLE GATE ARRAYBase Number Matches：1

A3P250-PQ208IY 数据手册

 浏览型号A3P250-PQ208IY的Datasheet PDF文件第2页浏览型号A3P250-PQ208IY的Datasheet PDF文件第3页浏览型号A3P250-PQ208IY的Datasheet PDF文件第4页浏览型号A3P250-PQ208IY的Datasheet PDF文件第5页浏览型号A3P250-PQ208IY的Datasheet PDF文件第6页浏览型号A3P250-PQ208IY的Datasheet PDF文件第7页 
Revision 18  
DS0097  
ProASIC3 Flash Family FPGAs  
with Optional Soft ARM Support  
Advanced I/O  
Features and Benefits  
•
•
•
700 Mbps DDR, LVDS-Capable I/Os (A3P250 and above)  
High Capacity  
1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation  
Wide Range Power Supply Voltage Support per JESD8-B,  
Allowing I/Os to Operate from 2.7 V to 3.6 V  
•
•
•
15 K to 1 M System Gates  
Up to 144 Kbits of True Dual-Port SRAM  
Up to 300 User I/Os  
•
•
Bank-Selectable I/O Voltages—up to 4 Banks per Chip  
Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /  
Reprogrammable Flash Technology  
†
2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X and LVCMOS  
•
130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS  
Process  
2.5 V / 5.0 V Input  
•
Differential I/O Standards: LVPECL, LVDS, B-LVDS, and  
M-LVDS (A3P250 and above)  
•
•
•
Instant On Level 0 Support  
Single-Chip Solution  
Retains Programmed Design when Powered Off  
•
•
•
•
•
•
I/O Registers on Input, Output, and Enable Paths  
‡
Hot-Swappable and Cold Sparing I/Os  
High Performance  
†
Programmable Output Slew Rate and Drive Strength  
•
•
350 MHz System Performance  
Weak Pull-Up/-Down  
†
3.3 V, 66 MHz 64-Bit PCI  
IEEE 1149.1 (JTAG) Boundary Scan Test  
Pin-Compatible Packages across the ProASIC3 Family  
In-System Programming (ISP) and Security  
Clock Conditioning Circuit (CCC) and PLL†  
•
ISP Using On-Chip 128-Bit Advanced Encryption Standard  
®
®
(AES) Decryption (except ARM -enabled ProASIC 3 devices)  
•
•
Six CCC Blocks, One with an Integrated PLL  
Configurable Phase-Shift, Multiply/Divide, Delay Capabilities  
and External Feedback  
†
via JTAG (IEEE 1532–compliant)  
®
•
FlashLock to Secure FPGA Contents  
Low Power  
•
Wide Input Frequency Range (1.5 MHz to 350 MHz)  
Embedded Memory†  
•
•
•
Core Voltage for Low Power  
Support for 1.5 V-Only Systems  
Low-Impedance Flash Switches  
•
•
1 Kbit of FlashROM User Nonvolatile Memory  
SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM  
†
High-Performance Routing Hierarchy  
Blocks (×1, ×2, ×4, ×9, and ×18 organizations)  
•
Segmented, Hierarchical Routing and Clock Structure  
•
True Dual-Port SRAM (except ×18)  
ARM Processor Support in ProASIC3 FPGAs  
®
®
•
M1 ProASIC3 Devices—ARM Cortex -M1 Soft Processor  
Available with or without Debug  
1
ProASIC3 Devices  
Cortex-M1 Devices  
System Gates  
A3P015  
A3P030  
A3P060 A3P125  
A3P250  
A3P400  
A3P600  
A3P1000  
2
M1A3P250 M1A3P400  
M1A3P600 M1A3P1000  
15,000  
30,000  
60,000 125,000  
250,000  
400,000  
600,000  
1,000,000  
Typical Equivalent Macrocells  
VersaTiles (D-flip-flops)  
RAM Kbits (1,024 bits)  
4,608-Bit Blocks  
128  
384  
–
256  
768  
–
512  
1,536  
18  
4
1,024  
3,072  
36  
2,048  
6,144  
36  
–
9,216  
54  
–
13,824  
108  
24  
–
24,576  
144  
32  
–
–
8
8
12  
FlashROM Kbits  
1
1
1
1
1
1
1
1
3
Secure (AES) ISP  
–
–
Yes  
1
Yes  
1
Yes  
1
Yes  
1
Yes  
1
Yes  
1
Integrated PLL in CCCs  
–
–
4
VersaNet Globals  
6
6
18  
2
18  
18  
18  
18  
18  
I/O Banks  
2
2
2
4
4
4
4
Maximum User I/Os  
49  
81  
96  
133  
157  
194  
235  
300  
Notes:  
1. A3P015 is not recommended for new designs.  
2. Refer to the Cortex-M1 product brief for more information.  
3. AES is not available for Cortex-M1 ProASIC3 devices.  
4. Six chip (main) and three quadrant global networks are available for A3P060 and above.  
5. The M1A3P250 device does not support this package.  
6. For higher densities and support of additional features, refer to the ProASIC3E Flash Family FPGAs datasheet.  
7. Package not available.  
† A3P015 and A3P030 devices do not support this feature.  
‡ Supported only by A3P015 and A3P030 devices.  
March 2016  
© 2016 Microsemi Corporation  
I
1234567...221

中文翻译

下载PDF

与A3P250-PQ208IY相关器件

型号 品牌 获取价格 描述 数据表
A3P250-PQ208Y MICROSEMI

获取价格

 		FPGA, 6144 CLBS, 250000 GATES, PQFP208, 28 X 28 MM, 3.40 MM HEIGHT, 0.50 MM PITCH, PLASTIC
A3P250-PQG100 MICROSEMI

获取价格

 		ProASIC3 Flash Family FPGAs with Optional Soft ARM Support
A3P250-PQG100ES MICROSEMI

获取价格

 		ProASIC3 Flash Family FPGAs with Optional Soft ARM Support
A3P250-PQG100I MICROSEMI

获取价格

 		ProASIC3 Flash Family FPGAs with Optional Soft ARM Support
A3P250-PQG100PP MICROSEMI

获取价格

 		ProASIC3 Flash Family FPGAs with Optional Soft ARM Support
A3P250-PQG100Y MICROSEMI

获取价格

 		ProASIC3 Flash Family FPGAs with Optional Soft ARM Support
A3P250-PQG100YES MICROSEMI

获取价格

 		ProASIC3 Flash Family FPGAs with Optional Soft ARM Support
A3P250-PQG100YI MICROSEMI

获取价格

 		ProASIC3 Flash Family FPGAs with Optional Soft ARM Support
A3P250-PQG100YPP MICROSEMI

获取价格

 		ProASIC3 Flash Family FPGAs with Optional Soft ARM Support
A3P250-PQG144 MICROSEMI

获取价格

 		ProASIC3 Flash Family FPGAs with Optional Soft ARM Support

与A3P250-PQ208IY相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证