Revision 3
Accelerator Series FPGAs – ACT 3 Family
• More than 500 Macro Functions
Features
• Replaces up to Twenty 32 Macro-Cell CPLDs
• Up to 10,000 Gate Array Equivalent Gates (up to 25,000
equivalent PLD Gates)
• Replaces up to One Hundred 20-Pin PAL® Packages
• Up to 1,153 Dedicated Flip-Flops
• VQFP, TQFP, BGA, and PQFP Packages
• Nonvolatile, User Programmable
• Fully Tested Prior to Shipment
• 5.0 V and 3.3 V Versions
• Optimized for Logic Synthesis Methodologies
• Low Power CMOS Technology
• Highly Predictable Performance with 100% Automatic Place-
and-Route
• As Low as 9.0 ns Clock-to-Output Times (–1 Speed Grade)
• Up to 186 MHz On-Chip Performance (–1 Speed Grade)
• Up to 228 User-Programmable I/O Pins
• Four Fast, Low-Skew Clock Networks
Table 1 • ACT 3 Family Product Information
Device
A1415
A1425
A1440
A1460
A14100
Capacity
Gate Array Equivalent Gates
1,500
3,750
40
2,500
6,250
60
4,000
10,000
100
6,000
15,000
150
10,000
25,000
250
PLD Equivalent Gates
TTL Equivalent Package (40 gates)
20-Pin PAL Equivalent Packages (100 gates)
Logic Modules
15
25
40
60
100
200
104
96
310
160
150
360
100
564
848
1,377
697
S-Module
288
432
C-Module
Dedicated Flip-Flops1
276
416
680
264
568
768
1,153
228
User I/Os (maximum)
80
140
168
Maximum Performance2 (worst-case commercial, –1 speed grade)
Chip-to-Chip3 (MHz)
80
47
80
47
80
47
78
47
76
47
Accumulators (16-bit, MHz)
Loadable Counter (16-bit, MHz)
Prescaled Loadable Counters (16-bit, MHz)
Datapath, Shift Registers (MHz)
Clock-to-Output (pad-to-pad, ns)
Packages4 (by pin count)
82
82
82
82
78
186
186
9.0
186
186
9.0
186
186
9.5
150
150
10.0
150
150
10.5
CPGA
PLCC
PQFP
RQFP
VQFP
TQFP
BGA
PG1005
PL84
PQ100
–
PG1335
PL84
PQ100, PQ160
PG1755
PL84
PQ160
–
VQ100
TQ176
–
PG207
PG257
–
PQ160, PQ208
–
–
–
–
VQ100
–
RQ208
–
VQ100
–
TQ176
BG2255
CQ196
–
–
–
–
–
BG313
CQ256
CQFP
CQ132
–
Notes:
1. One flip-flop per S0Module, two flip-flops per I/O Module.
2. Based on A1415A-1, A1425A-1, A1440A-1, A1460A-1, and A14100A-1.
3. Clock-to-Output (pad-to-pad) + assumed trace delay + setup time. Refer to the "System Performance Model" on page 1-1 and
Table 1-1 on page 1-2.
4. See the "Product Plan" table on page III for package availability.
5. Discontinued device and package combination.
6. –2 and –3 speed grades have been discontinued. For more information about discontinued devices, refer to the Product
Discontinuation Notices (PDNs) listed below, available on the Microsemi SoC Products Group website:
PDN March 2001, PDN 0104, PDN 0203, PDN 0604, PDN 1004
January 2012
I
© 2012 Microsemi Corporation